microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - decode1.vhdl
  13       - helpers.vhdl
  14       - decode2.vhdl
  15       - register_file.vhdl
  16       - cr_file.vhdl
  17       - crhelpers.vhdl
  18       - ppc_fx_insns.vhdl
  19       - sim_console.vhdl
  20       - logical.vhdl
  21       - countzero.vhdl
  22       - gpr_hazard.vhdl
  23       - cr_hazard.vhdl
  24       - control.vhdl
  25       - execute1.vhdl
  26       - loadstore1.vhdl
  27       - mmu.vhdl
  28       - dcache.vhdl
  29       - divider.vhdl
  30       - rotator.vhdl
  31       - writeback.vhdl
  32       - insn_helpers.vhdl
  33       - core.vhdl
  34       - icache.vhdl
  35       - plru.vhdl
  36       - cache_ram.vhdl
  37       - core_debug.vhdl
  38       - utils.vhdl
  39     file_type : vhdlSource-2008
  40
  41   soc:
  42     files:
  43       - wishbone_arbiter.vhdl
  44       - wishbone_debug_master.vhdl
  45       - wishbone_bram_wrapper.vhdl
  46       - soc.vhdl
  47       - xics.vhdl
  48       - syscon.vhdl
  49       - sync_fifo.vhdl
  50       - spi_rxtx.vhdl
  51       - spi_flash_ctrl.vhdl
  52     file_type : vhdlSource-2008
  53
  54   fpga:
  55     files:
  56       - fpga/main_bram.vhdl
  57       - fpga/soc_reset.vhdl
  58       - fpga/pp_fifo.vhd
  59       - fpga/pp_soc_uart.vhd
  60       - fpga/pp_utilities.vhd
  61       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  62     file_type : vhdlSource-2008
  63
  64   xilinx_specific:
  65     files:
  66       - xilinx-mult.vhdl : {file_type : vhdlSource-2008}
  67
  68   debug_xilinx:
  69     files:
  70       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  71
  72   debug_dummy:
  73     files:
  74       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  75
  76   nexys_a7:
  77     files:
  78       - fpga/nexys_a7.xdc : {file_type : xdc}
  79       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  80       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  81
  82   nexys_video:
  83     files:
  84       - fpga/nexys-video.xdc : {file_type : xdc}
  85       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  86       - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
  87
  88   arty_a7:
  89     files:
  90       - fpga/arty_a7.xdc : {file_type : xdc}
  91       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  92       - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
  93
  94   cmod_a7-35:
  95     files:
  96       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  97       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  98       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  99
 100   litedram:
 101       depend : [":microwatt:litedram"]
 102
 103   liteeth:
 104       depend : [":microwatt:liteeth"]
 105
 106   uart16550:
 107       depend : ["::uart16550"]
 108
 109 targets:
 110   nexys_a7:
 111     default_tool: vivado
 112     filesets: [core, nexys_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 113     parameters :
 114       - memory_size
 115       - ram_init_file
 116       - clk_input
 117       - clk_frequency
 118       - disable_flatten_core
 119       - log_length=2048
 120       - uart_is_16550
 121     tools:
 122       vivado: {part : xc7a100tcsg324-1}
 123     toplevel : toplevel
 124
 125   nexys_video-nodram:
 126     default_tool: vivado
 127     filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 128     parameters :
 129       - memory_size
 130       - ram_init_file
 131       - clk_input
 132       - clk_frequency
 133       - disable_flatten_core
 134       - spi_flash_offset=10485760
 135       - log_length=2048
 136       - uart_is_16550
 137     tools:
 138       vivado: {part : xc7a200tsbg484-1}
 139     toplevel : toplevel
 140
 141   nexys_video:
 142     default_tool: vivado
 143     filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 144     parameters:
 145       - memory_size
 146       - ram_init_file
 147       - use_litedram=true
 148       - disable_flatten_core
 149       - no_bram
 150       - spi_flash_offset=10485760
 151       - log_length=2048
 152       - uart_is_16550
 153     generate: [litedram_nexys_video]
 154     tools:
 155       vivado: {part : xc7a200tsbg484-1}
 156     toplevel : toplevel
 157
 158   arty_a7-35-nodram:
 159     default_tool: vivado
 160     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 161     parameters :
 162       - memory_size
 163       - ram_init_file
 164       - clk_input
 165       - clk_frequency
 166       - disable_flatten_core
 167       - spi_flash_offset=3145728
 168       - log_length=512
 169       - uart_is_16550
 170       - has_uart1
 171     tools:
 172       vivado: {part : xc7a35ticsg324-1L}
 173     toplevel : toplevel
 174
 175   arty_a7-35:
 176     default_tool: vivado
 177     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
 178     parameters :
 179       - memory_size
 180       - ram_init_file
 181       - use_litedram=true
 182       - use_liteeth=true
 183       - disable_flatten_core
 184       - no_bram
 185       - spi_flash_offset=3145728
 186       - log_length=512
 187       - uart_is_16550
 188       - has_uart1
 189     generate: [litedram_arty, liteeth_arty]
 190     tools:
 191       vivado: {part : xc7a35ticsg324-1L}
 192     toplevel : toplevel
 193
 194   arty_a7-100-nodram:
 195     default_tool: vivado
 196     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 197     parameters :
 198       - memory_size
 199       - ram_init_file
 200       - clk_input
 201       - clk_frequency
 202       - disable_flatten_core
 203       - spi_flash_offset=4194304
 204       - log_length=2048
 205       - uart_is_16550
 206       - has_uart1
 207     tools:
 208       vivado: {part : xc7a100ticsg324-1L}
 209     toplevel : toplevel
 210
 211   arty_a7-100:
 212     default_tool: vivado
 213     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
 214     parameters:
 215       - memory_size
 216       - ram_init_file
 217       - use_litedram=true
 218       - use_liteeth=true
 219       - disable_flatten_core
 220       - no_bram
 221       - spi_flash_offset=4194304
 222       - log_length=2048
 223       - uart_is_16550
 224       - has_uart1
 225     generate: [litedram_arty, liteeth_arty]
 226     tools:
 227       vivado: {part : xc7a100ticsg324-1L}
 228     toplevel : toplevel
 229
 230   cmod_a7-35:
 231     default_tool: vivado
 232     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 233     parameters :
 234       - memory_size
 235       - ram_init_file
 236       - reset_low=false
 237       - clk_input=12000000
 238       - clk_frequency
 239       - disable_flatten_core
 240       - log_length=512
 241       - uart_is_16550
 242     tools:
 243       vivado: {part : xc7a35tcpg236-1}
 244     toplevel : toplevel
 245
 246   synth:
 247     filesets: [core, soc, xilinx_specific]
 248     tools:
 249       vivado: {pnr : none}
 250     toplevel: core
 251
 252 generate:
 253   litedram_arty:
 254     generator: litedram_gen
 255     parameters: {board : arty}
 256
 257   liteeth_arty:
 258     generator: liteeth_gen
 259     parameters: {board : arty}
 260
 261   litedram_nexys_video:
 262     generator: litedram_gen
 263     parameters: {board : nexys-video}
 264
 265 parameters:
 266   memory_size:
 267     datatype    : int
 268     description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
 269     paramtype   : generic
 270     default     : 16384
 271
 272   ram_init_file:
 273     datatype    : file
 274     description : Initial on-chip RAM contents
 275     paramtype   : generic
 276
 277   reset_low:
 278     datatype    : bool
 279     description : External reset button polarity
 280     paramtype   : generic
 281
 282   clk_input:
 283     datatype    : int
 284     description : Clock input frequency in HZ (for top-generic based boards)
 285     paramtype   : generic
 286     default     : 100000000
 287
 288   clk_frequency:
 289     datatype    : int
 290     description : Generated system clock frequency in HZ (for top-generic based boards)
 291     paramtype   : generic
 292     default     : 100000000
 293
 294   disable_flatten_core:
 295     datatype    : bool
 296     description : Prevent Vivado from flattening the main core components
 297     paramtype   : generic
 298     default     : false
 299
 300   use_litedram:
 301     datatype    : bool
 302     description : Use liteDRAM
 303     paramtype   : generic
 304     default     : false
 305
 306   use_liteeth:
 307     datatype    : bool
 308     description : Use liteEth
 309     paramtype   : generic
 310     default     : false
 311
 312   uart_is_16550:
 313     datatype    : bool
 314     description : Use 16550-compatible UART from OpenCores
 315     paramtype   : generic
 316     default     : true
 317
 318   has_uart1:
 319     datatype    : bool
 320     description : Enable second UART (always 16550-compatible)
 321     paramtype   : generic
 322     default     : false
 323
 324   no_bram:
 325     datatype    : bool
 326     description : No internal block RAM (only DRAM and init code carrying payload)
 327     paramtype   : generic
 328     default     : false
 329
 330   spi_flash_offset:
 331     datatype    : int
 332     description : Offset (in bytes) in the SPI flash of the code payload to run
 333     paramtype   : generic
 334
 335   log_length:
 336     datatype    : int
 337     description : Length of the core log buffer in entries (32 bytes each)
 338     paramtype   : generic