38 file_type : vhdlSource-2008
42 - wishbone_arbiter.vhdl
43 - wishbone_debug_master.vhdl
44 - wishbone_bram_wrapper.vhdl
51 file_type : vhdlSource-2008
58 - fpga/pp_soc_uart.vhd
59 - fpga/pp_utilities.vhd
60 - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
61 file_type : vhdlSource-2008
65 - xilinx-mult.vhdl : {file_type : vhdlSource-2008}
66 - fpga/fpga-random.vhdl : {file_type : vhdlSource-2008}
67 - fpga/fpga-random.xdc : {file_type : xdc}
71 - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
75 - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
79 - fpga/nexys_a7.xdc : {file_type : xdc}
80 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
81 - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
85 - fpga/nexys-video.xdc : {file_type : xdc}
86 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
87 - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
91 - fpga/acorn-cle-215.xdc : {file_type : xdc}
92 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
93 - fpga/top-acorn-cle-215.vhdl : {file_type : vhdlSource-2008}
97 - fpga/genesys2.xdc : {file_type : xdc}
98 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
99 - fpga/top-genesys2.vhdl : {file_type : vhdlSource-2008}
103 - fpga/arty_a7.xdc : {file_type : xdc}
104 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
105 - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
109 - fpga/cmod_a7-35.xdc : {file_type : xdc}
110 - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
111 - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
114 depend : [":microwatt:litedram"]
117 depend : [":microwatt:liteeth"]
120 depend : ["::uart16550"]
125 filesets: [core, nexys_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
131 - disable_flatten_core
137 vivado: {part : xc7a100tcsg324-1}
140 acorn-cle-215-nodram:
142 filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
148 - disable_flatten_core
149 - spi_flash_offset=10485760
153 vivado: {part : xc7a200tsbg484-2}
158 filesets: [core, genesys2, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
165 - disable_flatten_core
166 - spi_flash_offset=10485760
168 - uart_is_16550=false
170 vivado: {part : xc7k325tffg900-2}
175 filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
180 - disable_flatten_core
182 - spi_flash_offset=10485760
185 generate: [litedram_acorn_cle_215]
187 vivado: {part : xc7a200tsbg484-2}
192 filesets: [core, genesys2, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
197 - disable_flatten_core
199 - spi_flash_offset=10485760
201 - uart_is_16550=false
202 generate: [litedram_genesys2]
204 vivado: {part : xc7k325tffg900-2}
209 filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
215 - disable_flatten_core
216 - spi_flash_offset=10485760
222 vivado: {part : xc7a200tsbg484-1}
227 filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
232 - disable_flatten_core
234 - spi_flash_offset=10485760
239 generate: [litedram_nexys_video]
241 vivado: {part : xc7a200tsbg484-1}
246 filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
252 - disable_flatten_core
253 - spi_flash_offset=3145728
260 vivado: {part : xc7a35ticsg324-1L}
265 filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
271 - disable_flatten_core
273 - spi_flash_offset=3145728
279 generate: [litedram_arty, liteeth_arty]
281 vivado: {part : xc7a35ticsg324-1L}
286 filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
292 - disable_flatten_core
293 - spi_flash_offset=4194304
300 vivado: {part : xc7a100ticsg324-1L}
305 filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
311 - disable_flatten_core
313 - spi_flash_offset=4194304
319 generate: [litedram_arty, liteeth_arty]
321 vivado: {part : xc7a100ticsg324-1L}
326 filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
333 - disable_flatten_core
339 vivado: {part : xc7a35tcpg236-1}
343 filesets: [core, soc, xilinx_specific]
350 generator: litedram_gen
351 parameters: {board : arty}
354 generator: liteeth_gen
355 parameters: {board : arty}
357 litedram_nexys_video:
358 generator: litedram_gen
359 parameters: {board : nexys-video}
361 litedram_acorn_cle_215:
362 generator: litedram_gen
363 parameters: {board : acorn-cle-215}
366 generator: litedram_gen
367 parameters: {board : genesys2}
372 description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
378 description : Initial on-chip RAM contents
383 description : External reset button polarity
388 description : Clock input frequency in HZ (for top-generic based boards)
394 description : Generated system clock frequency in HZ (for top-generic based boards)
400 description : Include a floating-point unit in the core
406 description : Include a branch target cache in the core
410 disable_flatten_core:
412 description : Prevent Vivado from flattening the main core components
418 description : Use liteDRAM
424 description : Use liteEth
430 description : Use 16550-compatible UART from OpenCores
436 description : Enable second UART (always 16550-compatible)
442 description : No internal block RAM (only DRAM and init code carrying payload)
448 description : Offset (in bytes) in the SPI flash of the code payload to run
453 description : Length of the core log buffer in entries (32 bytes each)