40 file_type : vhdlSource-2008
44 - wishbone_arbiter.vhdl
45 - wishbone_debug_master.vhdl
46 - wishbone_bram_wrapper.vhdl
53 file_type : vhdlSource-2008
60 - fpga/pp_soc_uart.vhd
61 - fpga/pp_utilities.vhd
62 - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
63 file_type : vhdlSource-2008
67 - xilinx-mult.vhdl : {file_type : vhdlSource-2008}
68 - fpga/fpga-random.vhdl : {file_type : vhdlSource-2008}
69 - fpga/fpga-random.xdc : {file_type : xdc}
73 - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
77 - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
81 - fpga/nexys_a7.xdc : {file_type : xdc}
82 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
83 - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
87 - fpga/nexys-video.xdc : {file_type : xdc}
88 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
89 - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
93 - fpga/acorn-cle-215.xdc : {file_type : xdc}
94 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
95 - fpga/top-acorn-cle-215.vhdl : {file_type : vhdlSource-2008}
99 - fpga/genesys2.xdc : {file_type : xdc}
100 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
101 - fpga/top-genesys2.vhdl : {file_type : vhdlSource-2008}
105 - fpga/arty_a7.xdc : {file_type : xdc}
106 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
107 - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
111 - fpga/cmod_a7-35.xdc : {file_type : xdc}
112 - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
113 - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
116 depend : [":microwatt:litedram"]
119 depend : [":microwatt:liteeth"]
122 depend : ["::uart16550"]
127 filesets: [core, nexys_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
133 - disable_flatten_core
138 vivado: {part : xc7a100tcsg324-1}
141 acorn-cle-215-nodram:
143 filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
149 - disable_flatten_core
150 - spi_flash_offset=10485760
154 vivado: {part : xc7a200tsbg484-2}
159 filesets: [core, genesys2, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
166 - disable_flatten_core
167 - spi_flash_offset=10485760
169 - uart_is_16550=false
171 vivado: {part : xc7k325tffg900-2}
176 filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
181 - disable_flatten_core
183 - spi_flash_offset=10485760
186 generate: [litedram_acorn_cle_215]
188 vivado: {part : xc7a200tsbg484-2}
193 filesets: [core, genesys2, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
198 - disable_flatten_core
200 - spi_flash_offset=10485760
202 - uart_is_16550=false
203 generate: [litedram_genesys2]
205 vivado: {part : xc7k325tffg900-2}
210 filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
216 - disable_flatten_core
217 - spi_flash_offset=10485760
222 vivado: {part : xc7a200tsbg484-1}
227 filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
232 - disable_flatten_core
234 - spi_flash_offset=10485760
238 generate: [litedram_nexys_video]
240 vivado: {part : xc7a200tsbg484-1}
245 filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
251 - disable_flatten_core
252 - spi_flash_offset=3145728
258 vivado: {part : xc7a35ticsg324-1L}
263 filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
269 - disable_flatten_core
271 - spi_flash_offset=3145728
276 generate: [litedram_arty, liteeth_arty]
278 vivado: {part : xc7a35ticsg324-1L}
283 filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
289 - disable_flatten_core
290 - spi_flash_offset=4194304
296 vivado: {part : xc7a100ticsg324-1L}
301 filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
307 - disable_flatten_core
309 - spi_flash_offset=4194304
314 generate: [litedram_arty, liteeth_arty]
316 vivado: {part : xc7a100ticsg324-1L}
321 filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
328 - disable_flatten_core
333 vivado: {part : xc7a35tcpg236-1}
337 filesets: [core, soc, xilinx_specific]
344 generator: litedram_gen
345 parameters: {board : arty}
348 generator: liteeth_gen
349 parameters: {board : arty}
351 litedram_nexys_video:
352 generator: litedram_gen
353 parameters: {board : nexys-video}
355 litedram_acorn_cle_215:
356 generator: litedram_gen
357 parameters: {board : acorn-cle-215}
360 generator: litedram_gen
361 parameters: {board : genesys2}
366 description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
372 description : Initial on-chip RAM contents
377 description : External reset button polarity
382 description : Clock input frequency in HZ (for top-generic based boards)
388 description : Generated system clock frequency in HZ (for top-generic based boards)
394 description : Include a floating-point unit in the core
398 disable_flatten_core:
400 description : Prevent Vivado from flattening the main core components
406 description : Use liteDRAM
412 description : Use liteEth
418 description : Use 16550-compatible UART from OpenCores
424 description : Enable second UART (always 16550-compatible)
430 description : No internal block RAM (only DRAM and init code carrying payload)
436 description : Offset (in bytes) in the SPI flash of the code payload to run
441 description : Length of the core log buffer in entries (32 bytes each)