microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - decode1.vhdl
  13       - helpers.vhdl
  14       - decode2.vhdl
  15       - register_file.vhdl
  16       - cr_file.vhdl
  17       - crhelpers.vhdl
  18       - ppc_fx_insns.vhdl
  19       - sim_console.vhdl
  20       - logical.vhdl
  21       - countzero.vhdl
  22       - gpr_hazard.vhdl
  23       - cr_hazard.vhdl
  24       - control.vhdl
  25       - execute1.vhdl
  26       - loadstore1.vhdl
  27       - mmu.vhdl
  28       - dcache.vhdl
  29       - multiply.vhdl
  30       - divider.vhdl
  31       - rotator.vhdl
  32       - writeback.vhdl
  33       - insn_helpers.vhdl
  34       - core.vhdl
  35       - icache.vhdl
  36       - plru.vhdl
  37       - cache_ram.vhdl
  38       - core_debug.vhdl
  39       - utils.vhdl
  40     file_type : vhdlSource-2008
  41
  42   soc:
  43     files:
  44       - wishbone_arbiter.vhdl
  45       - wishbone_debug_master.vhdl
  46       - wishbone_bram_wrapper.vhdl
  47       - soc.vhdl
  48       - xics.vhdl
  49       - syscon.vhdl
  50       - sync_fifo.vhdl
  51       - spi_rxtx.vhdl
  52       - spi_flash_ctrl.vhdl
  53     file_type : vhdlSource-2008
  54
  55   fpga:
  56     files:
  57       - fpga/main_bram.vhdl
  58       - fpga/soc_reset.vhdl
  59       - fpga/pp_fifo.vhd
  60       - fpga/pp_soc_uart.vhd
  61       - fpga/pp_utilities.vhd
  62       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  63     file_type : vhdlSource-2008
  64
  65   debug_xilinx:
  66     files:
  67       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  68
  69   debug_dummy:
  70     files:
  71       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  72
  73   nexys_a7:
  74     files:
  75       - fpga/nexys_a7.xdc : {file_type : xdc}
  76       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  77       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  78
  79   nexys_video:
  80     files:
  81       - fpga/nexys-video.xdc : {file_type : xdc}
  82       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  83       - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
  84
  85   arty_a7:
  86     files:
  87       - fpga/arty_a7.xdc : {file_type : xdc}
  88       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  89       - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
  90
  91   cmod_a7-35:
  92     files:
  93       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  94       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  95       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  96
  97   litedram:
  98       depend : [":microwatt:litedram"]
  99
 100 targets:
 101   nexys_a7:
 102     default_tool: vivado
 103     filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
 104     parameters :
 105       - memory_size
 106       - ram_init_file
 107       - clk_input
 108       - clk_frequency
 109       - disable_flatten_core
 110     tools:
 111       vivado: {part : xc7a100tcsg324-1}
 112     toplevel : toplevel
 113
 114   nexys_video-nodram:
 115     default_tool: vivado
 116     filesets: [core, nexys_video, soc, fpga, debug_xilinx]
 117     parameters :
 118       - memory_size
 119       - ram_init_file
 120       - clk_input
 121       - clk_frequency
 122       - disable_flatten_core
 123       - spi_flash_offset=10485760
 124     tools:
 125       vivado: {part : xc7a200tsbg484-1}
 126     toplevel : toplevel
 127
 128   nexys_video:
 129     default_tool: vivado
 130     filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram]
 131     parameters:
 132       - memory_size
 133       - ram_init_file
 134       - use_litedram=true
 135       - disable_flatten_core
 136       - no_bram
 137       - spi_flash_offset=10485760
 138     generate: [dram_nexys_video]
 139     tools:
 140       vivado: {part : xc7a200tsbg484-1}
 141     toplevel : toplevel
 142
 143   arty_a7-35-nodram:
 144     default_tool: vivado
 145     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 146     parameters :
 147       - memory_size
 148       - ram_init_file
 149       - clk_input
 150       - clk_frequency
 151       - disable_flatten_core
 152       - spi_flash_offset=3145728
 153     tools:
 154       vivado: {part : xc7a35ticsg324-1L}
 155     toplevel : toplevel
 156
 157   arty_a7-35:
 158     default_tool: vivado
 159     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
 160     parameters :
 161       - memory_size
 162       - ram_init_file
 163       - use_litedram=true
 164       - disable_flatten_core
 165       - no_bram
 166       - spi_flash_offset=3145728
 167     generate: [dram_arty]
 168     tools:
 169       vivado: {part : xc7a35ticsg324-1L}
 170     toplevel : toplevel
 171
 172   arty_a7-100-nodram:
 173     default_tool: vivado
 174     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 175     parameters :
 176       - memory_size
 177       - ram_init_file
 178       - clk_input
 179       - clk_frequency
 180       - disable_flatten_core
 181       - spi_flash_offset=4194304
 182     tools:
 183       vivado: {part : xc7a100ticsg324-1L}
 184     toplevel : toplevel
 185
 186   arty_a7-100:
 187     default_tool: vivado
 188     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
 189     parameters:
 190       - memory_size
 191       - ram_init_file
 192       - use_litedram=true
 193       - disable_flatten_core
 194       - no_bram
 195       - spi_flash_offset=4194304
 196     generate: [dram_arty]
 197     tools:
 198       vivado: {part : xc7a100ticsg324-1L}
 199     toplevel : toplevel
 200
 201   cmod_a7-35:
 202     default_tool: vivado
 203     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
 204     parameters :
 205       - memory_size
 206       - ram_init_file
 207       - reset_low=false
 208       - clk_input=12000000
 209       - clk_frequency
 210       - disable_flatten_core
 211     tools:
 212       vivado: {part : xc7a35tcpg236-1}
 213     toplevel : toplevel
 214
 215   synth:
 216     filesets: [core, soc]
 217     tools:
 218       vivado: {pnr : none}
 219     toplevel: core
 220
 221 generate:
 222   dram_arty:
 223     generator: litedram_gen
 224     parameters: {board : arty}
 225
 226   dram_nexys_video:
 227     generator: litedram_gen
 228     parameters: {board : nexys-video}
 229
 230 parameters:
 231   memory_size:
 232     datatype    : int
 233     description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
 234     paramtype   : generic
 235     default     : 16384
 236
 237   ram_init_file:
 238     datatype    : file
 239     description : Initial on-chip RAM contents
 240     paramtype   : generic
 241
 242   reset_low:
 243     datatype    : bool
 244     description : External reset button polarity
 245     paramtype   : generic
 246
 247   clk_input:
 248     datatype    : int
 249     description : Clock input frequency in HZ (for top-generic based boards)
 250     paramtype   : generic
 251     default     : 100000000
 252
 253   clk_frequency:
 254     datatype    : int
 255     description : Generated system clock frequency in HZ (for top-generic based boards)
 256     paramtype   : generic
 257     default     : 100000000
 258
 259   disable_flatten_core:
 260     datatype    : bool
 261     description : Prevent Vivado from flattening the main core components
 262     paramtype   : generic
 263     default     : false
 264
 265   use_litedram:
 266     datatype    : bool
 267     description : Use liteDRAM
 268     paramtype   : generic
 269     default     : false
 270
 271   no_bram:
 272     datatype    : bool
 273     description : No internal block RAM (only DRAM and init code carrying payload)
 274     paramtype   : generic
 275     default     : false
 276
 277   spi_flash_offset:
 278     datatype    : int
 279     description : Offset (in bytes) in the SPI flash of the code payload to run
 280     paramtype   : generic