40 file_type : vhdlSource-2008
44 - wishbone_arbiter.vhdl
45 - wishbone_debug_master.vhdl
46 - wishbone_bram_wrapper.vhdl
53 file_type : vhdlSource-2008
60 - fpga/pp_soc_uart.vhd
61 - fpga/pp_utilities.vhd
62 - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
63 file_type : vhdlSource-2008
67 - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
71 - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
75 - fpga/nexys_a7.xdc : {file_type : xdc}
76 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
77 - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
81 - fpga/nexys-video.xdc : {file_type : xdc}
82 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
83 - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
87 - fpga/arty_a7.xdc : {file_type : xdc}
88 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
89 - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
93 - fpga/cmod_a7-35.xdc : {file_type : xdc}
94 - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
95 - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
98 depend : [":microwatt:litedram"]
103 filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
109 - disable_flatten_core
111 vivado: {part : xc7a100tcsg324-1}
116 filesets: [core, nexys_video, soc, fpga, debug_xilinx]
122 - disable_flatten_core
123 - spi_flash_offset=10485760
125 vivado: {part : xc7a200tsbg484-1}
130 filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram]
135 - disable_flatten_core
137 - spi_flash_offset=10485760
138 generate: [dram_nexys_video]
140 vivado: {part : xc7a200tsbg484-1}
145 filesets: [core, arty_a7, soc, fpga, debug_xilinx]
151 - disable_flatten_core
152 - spi_flash_offset=3145728
154 vivado: {part : xc7a35ticsg324-1L}
159 filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
164 - disable_flatten_core
166 - spi_flash_offset=3145728
167 generate: [dram_arty]
169 vivado: {part : xc7a35ticsg324-1L}
174 filesets: [core, arty_a7, soc, fpga, debug_xilinx]
180 - disable_flatten_core
181 - spi_flash_offset=4194304
183 vivado: {part : xc7a100ticsg324-1L}
188 filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
193 - disable_flatten_core
195 - spi_flash_offset=4194304
196 generate: [dram_arty]
198 vivado: {part : xc7a100ticsg324-1L}
203 filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
210 - disable_flatten_core
212 vivado: {part : xc7a35tcpg236-1}
216 filesets: [core, soc]
223 generator: litedram_gen
224 parameters: {board : arty}
227 generator: litedram_gen
228 parameters: {board : nexys-video}
233 description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
239 description : Initial on-chip RAM contents
244 description : External reset button polarity
249 description : Clock input frequency in HZ (for top-generic based boards)
255 description : Generated system clock frequency in HZ (for top-generic based boards)
259 disable_flatten_core:
261 description : Prevent Vivado from flattening the main core components
267 description : Use liteDRAM
273 description : No internal block RAM (only DRAM and init code carrying payload)
279 description : Offset (in bytes) in the SPI flash of the code payload to run