microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - fetch2.vhdl
  13       - decode1.vhdl
  14       - helpers.vhdl
  15       - decode2.vhdl
  16       - register_file.vhdl
  17       - cr_file.vhdl
  18       - crhelpers.vhdl
  19       - ppc_fx_insns.vhdl
  20       - sim_console.vhdl
  21       - logical.vhdl
  22       - countzero.vhdl
  23       - gpr_hazard.vhdl
  24       - cr_hazard.vhdl
  25       - control.vhdl
  26       - execute1.vhdl
  27       - loadstore1.vhdl
  28       - mmu.vhdl
  29       - dcache.vhdl
  30       - multiply.vhdl
  31       - divider.vhdl
  32       - rotator.vhdl
  33       - writeback.vhdl
  34       - insn_helpers.vhdl
  35       - core.vhdl
  36       - icache.vhdl
  37       - plru.vhdl
  38       - cache_ram.vhdl
  39       - core_debug.vhdl
  40       - utils.vhdl
  41     file_type : vhdlSource-2008
  42
  43   soc:
  44     files:
  45       - wishbone_arbiter.vhdl
  46       - wishbone_debug_master.vhdl
  47       - wishbone_bram_wrapper.vhdl
  48       - soc.vhdl
  49       - xics.vhdl
  50       - syscon.vhdl
  51       - sync_fifo.vhdl
  52     file_type : vhdlSource-2008
  53
  54   fpga:
  55     files:
  56       - fpga/main_bram.vhdl
  57       - fpga/soc_reset.vhdl
  58       - fpga/pp_fifo.vhd
  59       - fpga/pp_soc_uart.vhd
  60       - fpga/pp_utilities.vhd
  61       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  62     file_type : vhdlSource-2008
  63
  64   debug_xilinx:
  65     files:
  66       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  67
  68   debug_dummy:
  69     files:
  70       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  71
  72   nexys_a7:
  73     files:
  74       - fpga/nexys_a7.xdc : {file_type : xdc}
  75       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  76       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  77
  78   nexys_video:
  79     files:
  80       - fpga/nexys-video.xdc : {file_type : xdc}
  81       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  82       - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
  83
  84   arty_a7:
  85     files:
  86       - fpga/arty_a7.xdc : {file_type : xdc}
  87       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  88       - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
  89
  90   cmod_a7-35:
  91     files:
  92       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  93       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  94       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  95
  96   litedram:
  97       depend : [":microwatt:litedram"]
  98
  99 targets:
 100   nexys_a7:
 101     default_tool: vivado
 102     filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
 103     parameters :
 104       - memory_size
 105       - ram_init_file
 106       - clk_input
 107       - clk_frequency
 108       - disable_flatten_core
 109     tools:
 110       vivado: {part : xc7a100tcsg324-1}
 111     toplevel : toplevel
 112
 113   nexys_video-nodram:
 114     default_tool: vivado
 115     filesets: [core, nexys_video, soc, fpga, debug_xilinx]
 116     parameters :
 117       - memory_size
 118       - ram_init_file
 119       - clk_input
 120       - clk_frequency
 121       - disable_flatten_core
 122     tools:
 123       vivado: {part : xc7a200tsbg484-1}
 124     toplevel : toplevel
 125
 126   nexys_video:
 127     default_tool: vivado
 128     filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram]
 129     parameters:
 130       - memory_size
 131       - ram_init_file
 132       - use_litedram=true
 133       - disable_flatten_core
 134       - no_bram
 135     generate: [dram_nexys_video]
 136     tools:
 137       vivado: {part : xc7a200tsbg484-1}
 138     toplevel : toplevel
 139
 140   arty_a7-35-nodram:
 141     default_tool: vivado
 142     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 143     parameters :
 144       - memory_size
 145       - ram_init_file
 146       - clk_input
 147       - clk_frequency
 148       - disable_flatten_core
 149     tools:
 150       vivado: {part : xc7a35ticsg324-1L}
 151     toplevel : toplevel
 152
 153   arty_a7-35:
 154     default_tool: vivado
 155     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
 156     parameters :
 157       - memory_size
 158       - ram_init_file
 159       - use_litedram=true
 160       - disable_flatten_core
 161       - no_bram
 162     generate: [dram_arty]
 163     tools:
 164       vivado: {part : xc7a35ticsg324-1L}
 165     toplevel : toplevel
 166
 167   arty_a7-100-nodram:
 168     default_tool: vivado
 169     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 170     parameters :
 171       - memory_size
 172       - ram_init_file
 173       - clk_input
 174       - clk_frequency
 175       - disable_flatten_core
 176     tools:
 177       vivado: {part : xc7a100ticsg324-1L}
 178     toplevel : toplevel
 179
 180   arty_a7-100:
 181     default_tool: vivado
 182     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
 183     parameters:
 184       - memory_size
 185       - ram_init_file
 186       - use_litedram=true
 187       - disable_flatten_core
 188       - no_bram
 189     generate: [dram_arty]
 190     tools:
 191       vivado: {part : xc7a100ticsg324-1L}
 192     toplevel : toplevel
 193
 194   cmod_a7-35:
 195     default_tool: vivado
 196     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
 197     parameters :
 198       - memory_size
 199       - ram_init_file
 200       - reset_low=false
 201       - clk_input=12000000
 202       - clk_frequency
 203       - disable_flatten_core
 204     tools:
 205       vivado: {part : xc7a35tcpg236-1}
 206     toplevel : toplevel
 207
 208   synth:
 209     filesets: [core, soc]
 210     tools:
 211       vivado: {pnr : none}
 212     toplevel: core
 213
 214 generate:
 215   dram_arty:
 216     generator: litedram_gen
 217     parameters: {board : arty}
 218
 219   dram_nexys_video:
 220     generator: litedram_gen
 221     parameters: {board : nexys-video}
 222
 223 parameters:
 224   memory_size:
 225     datatype    : int
 226     description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
 227     paramtype   : generic
 228     default     : 16384
 229
 230   ram_init_file:
 231     datatype    : file
 232     description : Initial on-chip RAM contents
 233     paramtype   : generic
 234
 235   reset_low:
 236     datatype    : bool
 237     description : External reset button polarity
 238     paramtype   : generic
 239
 240   clk_input:
 241     datatype    : int
 242     description : Clock input frequency in HZ (for top-generic based boards)
 243     paramtype   : generic
 244     default     : 100000000
 245
 246   clk_frequency:
 247     datatype    : int
 248     description : Generated system clock frequency in HZ (for top-generic based boards)
 249     paramtype   : generic
 250     default     : 100000000
 251
 252   disable_flatten_core:
 253     datatype    : bool
 254     description : Prevent Vivado from flattening the main core components
 255     paramtype   : generic
 256     default     : false
 257
 258   use_litedram:
 259     datatype    : bool
 260     description : Use liteDRAM
 261     paramtype   : generic
 262     default     : false
 263
 264   no_bram:
 265     datatype    : bool
 266     description : No internal block RAM (only DRAM and init code carrying payload)
 267     paramtype   : generic
 268     default     : false