Add FuseSoC core description file with Nexys A7 support
[microwatt.git] / microwatt.core
1 CAPI=2:
2
3 name : ::microwatt:0
4
5 filesets:
6 core:
7 files:
8 - decode_types.vhdl
9 - wishbone_types.vhdl
10 - common.vhdl
11 - fetch1.vhdl
12 - fetch2.vhdl
13 - decode1.vhdl
14 - helpers.vhdl
15 - decode2.vhdl
16 - register_file.vhdl
17 - cr_file.vhdl
18 - crhelpers.vhdl
19 - ppc_fx_insns.vhdl
20 - sim_console.vhdl
21 - execute1.vhdl
22 - execute2.vhdl
23 - loadstore1.vhdl
24 - loadstore2.vhdl
25 - multiply.vhdl
26 - writeback.vhdl
27 - wishbone_arbiter.vhdl
28 - core.vhdl
29 file_type : vhdlSource-2008
30
31 soc:
32 files:
33 - fpga/pp_fifo.vhd
34 - fpga/pp_soc_memory.vhd
35 - fpga/pp_soc_reset.vhd
36 - fpga/pp_soc_uart.vhd
37 - fpga/pp_utilities.vhd
38 - fpga/toplevel.vhd
39 - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
40 file_type : vhdlSource-2008
41
42 nexys_a7:
43 files:
44 - fpga/nexys_a7.xdc : {file_type : xdc}
45 - fpga/clk_gen_bypass.vhd : {file_type : vhdlSource-2008}
46
47 targets:
48 nexys_a7:
49 default_tool: vivado
50 filesets: [core, nexys_a7, soc]
51 parameters : [memory_size, ram_init_file]
52 tools:
53 vivado: {part : xc7a100tcsg324-1}
54 toplevel : toplevel
55
56 parameters:
57 memory_size:
58 datatype : int
59 description : On-chip memory size (bytes)
60 paramtype : generic
61
62 ram_init_file:
63 datatype : file
64 description : Initial on-chip RAM contents
65 paramtype : generic