microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - fetch2.vhdl
  13       - decode1.vhdl
  14       - helpers.vhdl
  15       - decode2.vhdl
  16       - register_file.vhdl
  17       - cr_file.vhdl
  18       - crhelpers.vhdl
  19       - ppc_fx_insns.vhdl
  20       - sim_console.vhdl
  21       - execute1.vhdl
  22       - execute2.vhdl
  23       - loadstore1.vhdl
  24       - loadstore2.vhdl
  25       - multiply.vhdl
  26       - writeback.vhdl
  27       - insn_helpers.vhdl
  28       - wishbone_debug_master.vhdl
  29       - core.vhdl
  30       - icache.vhdl
  31     file_type : vhdlSource-2008
  32
  33   soc:
  34     files:
  35       - wishbone_arbiter.vhdl
  36       - wishbone_debug_master.vhdl
  37       - soc.vhdl
  38     file_type : vhdlSource-2008
  39
  40   fpga:
  41     files:
  42       - fpga/pp_fifo.vhd
  43       - fpga/mw_soc_memory.vhdl
  44       - fpga/soc_reset.vhdl
  45       - fpga/pp_soc_uart.vhd
  46       - fpga/pp_utilities.vhd
  47       - fpga/toplevel.vhdl
  48       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  49     file_type : vhdlSource-2008
  50
  51   debug_xilinx:
  52     files:
  53       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  54
  55   debug_dummy:
  56     files:
  57       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  58
  59   nexys_a7:
  60     files:
  61       - fpga/nexys_a7.xdc : {file_type : xdc}
  62       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  63
  64   nexys_video:
  65     files:
  66       - fpga/nexys-video.xdc : {file_type : xdc}
  67       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  68
  69   arty_a7-35:
  70     files:
  71       - fpga/arty_a7-35.xdc : {file_type : xdc}
  72       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  73
  74   cmod_a7-35:
  75     files:
  76       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  77       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  78
  79 targets:
  80   nexys_a7:
  81     default_tool: vivado
  82     filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
  83     parameters : [memory_size, ram_init_file]
  84     tools:
  85       vivado: {part : xc7a100tcsg324-1}
  86     toplevel : toplevel
  87
  88   nexys_video:
  89     default_tool: vivado
  90     filesets: [core, nexys_video, soc, fpga, debug_xilinx]
  91     parameters : [memory_size, ram_init_file]
  92     tools:
  93       vivado: {part : xc7a200tsbg484-1}
  94     toplevel : toplevel
  95
  96   arty_a7-35:
  97     default_tool: vivado
  98     filesets: [core, arty_a7-35, soc, fpga, debug_xilinx]
  99     parameters : [memory_size, ram_init_file]
 100     tools:
 101       vivado: {part : xc7a35ticsg324-1L}
 102     toplevel : toplevel
 103
 104   cmod_a7-35:
 105     default_tool: vivado
 106     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
 107     parameters : [memory_size, ram_init_file, reset_low=false]
 108     tools:
 109       vivado: {part : xc7a35tcpg236-1}
 110     toplevel : toplevel
 111
 112   synth:
 113     filesets: [core, soc]
 114     tools:
 115       vivado: {pnr : none}
 116     toplevel: core
 117
 118 parameters:
 119   memory_size:
 120     datatype    : int
 121     description : On-chip memory size (bytes)
 122     paramtype   : generic
 123
 124   ram_init_file:
 125     datatype    : file
 126     description : Initial on-chip RAM contents
 127     paramtype   : generic
 128
 129   reset_low:
 130     datatype    : bool
 131     description : External reset button polarity
 132     paramtype   : generic