Merge pull request #204 from ozbenh/spi
[microwatt.git] / microwatt.core
1 CAPI=2:
2
3 name : ::microwatt:0
4
5 filesets:
6 core:
7 files:
8 - decode_types.vhdl
9 - wishbone_types.vhdl
10 - common.vhdl
11 - fetch1.vhdl
12 - fetch2.vhdl
13 - decode1.vhdl
14 - helpers.vhdl
15 - decode2.vhdl
16 - register_file.vhdl
17 - cr_file.vhdl
18 - crhelpers.vhdl
19 - ppc_fx_insns.vhdl
20 - sim_console.vhdl
21 - logical.vhdl
22 - countzero.vhdl
23 - gpr_hazard.vhdl
24 - cr_hazard.vhdl
25 - control.vhdl
26 - execute1.vhdl
27 - loadstore1.vhdl
28 - mmu.vhdl
29 - dcache.vhdl
30 - multiply.vhdl
31 - divider.vhdl
32 - rotator.vhdl
33 - writeback.vhdl
34 - insn_helpers.vhdl
35 - core.vhdl
36 - icache.vhdl
37 - plru.vhdl
38 - cache_ram.vhdl
39 - core_debug.vhdl
40 - utils.vhdl
41 file_type : vhdlSource-2008
42
43 soc:
44 files:
45 - wishbone_arbiter.vhdl
46 - wishbone_debug_master.vhdl
47 - wishbone_bram_wrapper.vhdl
48 - soc.vhdl
49 - xics.vhdl
50 - syscon.vhdl
51 - sync_fifo.vhdl
52 - spi_rxtx.vhdl
53 - spi_flash_ctrl.vhdl
54 file_type : vhdlSource-2008
55
56 fpga:
57 files:
58 - fpga/main_bram.vhdl
59 - fpga/soc_reset.vhdl
60 - fpga/pp_fifo.vhd
61 - fpga/pp_soc_uart.vhd
62 - fpga/pp_utilities.vhd
63 - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
64 file_type : vhdlSource-2008
65
66 debug_xilinx:
67 files:
68 - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
69
70 debug_dummy:
71 files:
72 - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
73
74 nexys_a7:
75 files:
76 - fpga/nexys_a7.xdc : {file_type : xdc}
77 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
78 - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
79
80 nexys_video:
81 files:
82 - fpga/nexys-video.xdc : {file_type : xdc}
83 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
84 - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
85
86 arty_a7:
87 files:
88 - fpga/arty_a7.xdc : {file_type : xdc}
89 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
90 - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
91
92 cmod_a7-35:
93 files:
94 - fpga/cmod_a7-35.xdc : {file_type : xdc}
95 - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
96 - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
97
98 litedram:
99 depend : [":microwatt:litedram"]
100
101 targets:
102 nexys_a7:
103 default_tool: vivado
104 filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
105 parameters :
106 - memory_size
107 - ram_init_file
108 - clk_input
109 - clk_frequency
110 - disable_flatten_core
111 tools:
112 vivado: {part : xc7a100tcsg324-1}
113 toplevel : toplevel
114
115 nexys_video-nodram:
116 default_tool: vivado
117 filesets: [core, nexys_video, soc, fpga, debug_xilinx]
118 parameters :
119 - memory_size
120 - ram_init_file
121 - clk_input
122 - clk_frequency
123 - disable_flatten_core
124 - spi_flash_offset=10485760
125 tools:
126 vivado: {part : xc7a200tsbg484-1}
127 toplevel : toplevel
128
129 nexys_video:
130 default_tool: vivado
131 filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram]
132 parameters:
133 - memory_size
134 - ram_init_file
135 - use_litedram=true
136 - disable_flatten_core
137 - no_bram
138 - spi_flash_offset=10485760
139 generate: [dram_nexys_video]
140 tools:
141 vivado: {part : xc7a200tsbg484-1}
142 toplevel : toplevel
143
144 arty_a7-35-nodram:
145 default_tool: vivado
146 filesets: [core, arty_a7, soc, fpga, debug_xilinx]
147 parameters :
148 - memory_size
149 - ram_init_file
150 - clk_input
151 - clk_frequency
152 - disable_flatten_core
153 - spi_flash_offset=3145728
154 tools:
155 vivado: {part : xc7a35ticsg324-1L}
156 toplevel : toplevel
157
158 arty_a7-35:
159 default_tool: vivado
160 filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
161 parameters :
162 - memory_size
163 - ram_init_file
164 - use_litedram=true
165 - disable_flatten_core
166 - no_bram
167 - spi_flash_offset=3145728
168 generate: [dram_arty]
169 tools:
170 vivado: {part : xc7a35ticsg324-1L}
171 toplevel : toplevel
172
173 arty_a7-100-nodram:
174 default_tool: vivado
175 filesets: [core, arty_a7, soc, fpga, debug_xilinx]
176 parameters :
177 - memory_size
178 - ram_init_file
179 - clk_input
180 - clk_frequency
181 - disable_flatten_core
182 - spi_flash_offset=4194304
183 tools:
184 vivado: {part : xc7a100ticsg324-1L}
185 toplevel : toplevel
186
187 arty_a7-100:
188 default_tool: vivado
189 filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
190 parameters:
191 - memory_size
192 - ram_init_file
193 - use_litedram=true
194 - disable_flatten_core
195 - no_bram
196 - spi_flash_offset=4194304
197 generate: [dram_arty]
198 tools:
199 vivado: {part : xc7a100ticsg324-1L}
200 toplevel : toplevel
201
202 cmod_a7-35:
203 default_tool: vivado
204 filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
205 parameters :
206 - memory_size
207 - ram_init_file
208 - reset_low=false
209 - clk_input=12000000
210 - clk_frequency
211 - disable_flatten_core
212 tools:
213 vivado: {part : xc7a35tcpg236-1}
214 toplevel : toplevel
215
216 synth:
217 filesets: [core, soc]
218 tools:
219 vivado: {pnr : none}
220 toplevel: core
221
222 generate:
223 dram_arty:
224 generator: litedram_gen
225 parameters: {board : arty}
226
227 dram_nexys_video:
228 generator: litedram_gen
229 parameters: {board : nexys-video}
230
231 parameters:
232 memory_size:
233 datatype : int
234 description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
235 paramtype : generic
236 default : 16384
237
238 ram_init_file:
239 datatype : file
240 description : Initial on-chip RAM contents
241 paramtype : generic
242
243 reset_low:
244 datatype : bool
245 description : External reset button polarity
246 paramtype : generic
247
248 clk_input:
249 datatype : int
250 description : Clock input frequency in HZ (for top-generic based boards)
251 paramtype : generic
252 default : 100000000
253
254 clk_frequency:
255 datatype : int
256 description : Generated system clock frequency in HZ (for top-generic based boards)
257 paramtype : generic
258 default : 100000000
259
260 disable_flatten_core:
261 datatype : bool
262 description : Prevent Vivado from flattening the main core components
263 paramtype : generic
264 default : false
265
266 use_litedram:
267 datatype : bool
268 description : Use liteDRAM
269 paramtype : generic
270 default : false
271
272 no_bram:
273 datatype : bool
274 description : No internal block RAM (only DRAM and init code carrying payload)
275 paramtype : generic
276 default : false
277
278 spi_flash_offset:
279 datatype : int
280 description : Offset (in bytes) in the SPI flash of the code payload to run
281 paramtype : generic