41 file_type : vhdlSource-2008
45 - wishbone_arbiter.vhdl
46 - wishbone_debug_master.vhdl
47 - wishbone_bram_wrapper.vhdl
54 file_type : vhdlSource-2008
61 - fpga/pp_soc_uart.vhd
62 - fpga/pp_utilities.vhd
63 - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
64 file_type : vhdlSource-2008
68 - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
72 - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
76 - fpga/nexys_a7.xdc : {file_type : xdc}
77 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
78 - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
82 - fpga/nexys-video.xdc : {file_type : xdc}
83 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
84 - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
88 - fpga/arty_a7.xdc : {file_type : xdc}
89 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
90 - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
94 - fpga/cmod_a7-35.xdc : {file_type : xdc}
95 - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
96 - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
99 depend : [":microwatt:litedram"]
104 filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
110 - disable_flatten_core
112 vivado: {part : xc7a100tcsg324-1}
117 filesets: [core, nexys_video, soc, fpga, debug_xilinx]
123 - disable_flatten_core
124 - spi_flash_offset=10485760
126 vivado: {part : xc7a200tsbg484-1}
131 filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram]
136 - disable_flatten_core
138 - spi_flash_offset=10485760
139 generate: [dram_nexys_video]
141 vivado: {part : xc7a200tsbg484-1}
146 filesets: [core, arty_a7, soc, fpga, debug_xilinx]
152 - disable_flatten_core
153 - spi_flash_offset=3145728
155 vivado: {part : xc7a35ticsg324-1L}
160 filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
165 - disable_flatten_core
167 - spi_flash_offset=3145728
168 generate: [dram_arty]
170 vivado: {part : xc7a35ticsg324-1L}
175 filesets: [core, arty_a7, soc, fpga, debug_xilinx]
181 - disable_flatten_core
182 - spi_flash_offset=4194304
184 vivado: {part : xc7a100ticsg324-1L}
189 filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
194 - disable_flatten_core
196 - spi_flash_offset=4194304
197 generate: [dram_arty]
199 vivado: {part : xc7a100ticsg324-1L}
204 filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
211 - disable_flatten_core
213 vivado: {part : xc7a35tcpg236-1}
217 filesets: [core, soc]
224 generator: litedram_gen
225 parameters: {board : arty}
228 generator: litedram_gen
229 parameters: {board : nexys-video}
234 description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
240 description : Initial on-chip RAM contents
245 description : External reset button polarity
250 description : Clock input frequency in HZ (for top-generic based boards)
256 description : Generated system clock frequency in HZ (for top-generic based boards)
260 disable_flatten_core:
262 description : Prevent Vivado from flattening the main core components
268 description : Use liteDRAM
274 description : No internal block RAM (only DRAM and init code carrying payload)
280 description : Offset (in bytes) in the SPI flash of the code payload to run