f776cdaca5fe87f9623ee5106fa26b75e160d9e8
[litex.git] / migen / build / platforms / apf51.py
1 from migen.build.generic_platform import *
2 from migen.build.xilinx import XilinxPlatform
3
4
5 _ios = [
6 ("clk3", 0, Pins("N8"), IOStandard("LVCMOS33")),
7 ("clko", 0, Pins("N7"), IOStandard("LVCMOS33")),
8 ("fpga_initb", 0, Pins("P3"), IOStandard("LVCMOS33")),
9 ("fpga_program", 0, Pins("R2"), IOStandard("LVCMOS33")),
10 ("eim", 0,
11 Subsignal("bclk", Pins("N12")),
12 Subsignal("eb1", Pins("P13")),
13 Subsignal("cs1", Pins("R11")),
14 Subsignal("cs2", Pins("N9")),
15 Subsignal("lba", Pins("R9")),
16 Subsignal("eb0", Pins("P7")),
17 Subsignal("oe", Pins("R7")),
18 Subsignal("rw", Pins("R6")),
19 Subsignal("dtack", Pins("N4")),
20 Subsignal("wait", Pins("R4")),
21 Subsignal("da", Pins("N6 L5 L6 R5 P5 N11 M11 P11 L8 K8 M8 M10 L9 R10 N5 M5")),
22 IOStandard("LVCMOS33")
23 )
24 ]
25
26 _connectors = [
27 ("J2",
28 "None", # No 0 pin
29 "None", # 1 FPGA Bank1 power
30 "None", # 2 FPGA Bank1 power
31 "None", # 3 GND
32 "B14", # 4 IO_L1P_A25_1
33 "B15", # 5 IO_L1N_A24_VREF_1
34 "C14", # 6 IO_L33P_A15_M1A10_1
35 "C15", # 7 IO_L33N_A14_M1A4_1
36 "D13", # 8 IO_L35P_A11_M1A7_1
37 "D15", # 9 IO_L35N_A10_M1A2_1
38 "E14", # 10 IO_L37P_A7_M1A0_1
39 "E15", # 11 IO_L37N_A6_M1A1_1
40 "None", # 12 GND
41 "F13", # 13 IO_L39P_M1A3_1
42 "F15", # 14 IO_L39N_M1ODT_1
43 "G14", # 15 IO_L41P_GCLK9_IRDY1_M1RASN_1
44 "G15", # 16 IO_L41N_GCLK8_M1CASN_1
45 "H13", # 17 IO_L42P_GCLK7_M1UDM_1
46 "H15", # 18 IO_L42N_GCLK6_TRDY1_M1LDM
47 "J14", # 19 IO_L43P_GCLK5_M1DQ4_1
48 "J15", # 20 IO_L43N_GCLK4_M1DQ5_1
49 "K13", # 21 IO_L44P_A3_M1DQ6_1
50 "K15", # 22 IO_L44N_A2_M1DQ7_1
51 "L14", # 23 IO_L45P_A1_M1LDQS_1
52 "L15", # 24 IO_L45N_A0_M1LDQSN_1
53 "None", # 25 GND
54 "E2", # 26 IO_L52P_M3A8_3
55 "E1", # 27 IO_L52N_M3A9_3
56 "D3", # 28 IO_L54P_M3RESET_3
57 "D1", # 29 IO_L54N_M3A11_3
58 "F3", # 30 IO_L46P_M3CLK_3
59 "F1", # 31 IO_L46N_M3CLKN_3
60 "G2", # 32 IO_L44P_GCLK21_M3A5_3
61 "G1", # 33 IO_L44N_GCLK20_M3A6_3
62 "H3", # 34 IO_L42P_GCLK25_TRDY2_M3UDM_3
63 "H1", # 35 IO_L42N_GCLK24_M3LDM_3
64 "K3", # 36 IO_L40P_M3DQ6_3
65 "K1", # 37 IO_L40N_M3DQ7_3
66 "None", # 38 GND
67 "None", # 39 GPIO4_16
68 "None", # 40 GPIO4_17
69 "None", # 41 BOOT_MODE0
70 "None", # 42 AUD5_RXFS
71 "None", # 43 AUD5_RXC
72 "None", # 44 GND
73 "None", # 45 AUD5_RXD
74 "None", # 46 AUD5_TXC
75 "None", # 47 AUD5_TXFS
76 "None", # 48 GND
77 "None", # 49 SPI2_SCLK_GPT_CMPOUT3
78 "None", # 50 SPI2_MISO
79 "None", # 51 SPI2_MOSI
80 "None", # 52 SPI2_SS1
81 "None", # 53 SPI2_SS2
82 "None", # 54 SPI2_SS3
83 "None", # 55 SPI2_RDY
84 "None", # 56 OWIRE
85 "None", # 57 GND
86 "None", # 58 SPI1_SCLK
87 "None", # 59 SPI1_MISO
88 "None", # 60 SPI1_MOSI
89 "None", # 61 SPI1_SS0
90 "None", # 62 SPI1_SS1
91 "None", # 63 SPI1_RDY
92 "None", # 64 RESET#
93 "None", # 65 VIO_H2
94 "None", # 66 PMIC_GPIO6
95 "None", # 67 TOUCH_X+
96 "None", # 68 TOUCH_X-
97 "None", # 69 TOUCH_Y+
98 "None", # 70 TOUCH_Y-
99 "None", # 71 AUXADCIN4
100 "None", # 72 AUXADCIN3
101 "None", # 73 AUXADCIN2
102 "None", # 74 AUXADCIN1
103 "None", # 75 PMIC_GPIO7
104 "None", # 76 +1v8
105 "None", # 77 RESERVED
106 "None", # 78 UART3_TXD
107 "None", # 79 UART_3_RXD
108 "None", # 80 UART2_TXD
109 "None", # 81 UART2_RXD
110 "None", # 82 UART2_RTS_KEY_COL7
111 "None", # 83 UART2_CTS_KEY_COL6
112 "None", # 84 UART1_TXD
113 "None", # 85 UART1_RXD
114 "None", # 86 UART1_RTS
115 "None", # 87 UART1_CTS
116 "None", # 88 GND
117 "None", # 89 AUD3_TXD
118 "None", # 90 AUD3_RXD
119 "None", # 91 AUD3_FS
120 "None", # 92 AUD3_CK
121 "None", # 93 GND
122 "None", # 94 AUD6_TXFS_KEY_ROW7
123 "None", # 95 AUD6_TXC_KEY_ROW6
124 "None", # 96 AUD6_RXD_KEY_ROW5
125 "None", # 97 AUD6_TXD_KEY_ROW4
126 "None", # 98 I2C2_SDA_UART3_CTS
127 "None", # 99 I2C2_SCL_UART3_RTS
128 "None", # 100 BOOT_MODE1
129 "None", # 101 PWM2
130 "None", # 102 PWM1
131 "None", # 103 GND
132 "L1", # 104 IO_L39N_M3LDQSN_3
133 "L2", # 105 IO_L39P_M3LDQS_3
134 "J1", # 106 IO_L41N_GCLK26_M3DQ5_3
135 "J2", # 107 IO_L41P_GCLK27_M3DQ4_3
136 "J3", # 108 IO_L43N_GCLK22_IRDY2_M3CASN_3
137 "K4", # 109 IO_L43P_GCLK23_M3RASN_3
138 "J4", # 110 IO_L45N_M3ODT_3
139 "K5", # 111 IO_L45P_M3A3_3
140 "C1", # 112 IO_L83N_VREF_3
141 "C2", # 113 IO_L83P_3
142 "E3", # 114 IO_L53N_M3A12_3
143 "D4", # 115 IO_L53P_M3CKE_3
144 "None", # 116 GND
145 "P15", # 117 IO_L74N_DOUT_BUSY_1
146 "P14", # 118 IO_L74P_AWAKE_1
147 "N15", # 119 IO_L47N_LDC_M1DQ1_1
148 "N14", # 120 IO_L47P_FWE_B_M1DQ0_1
149 "M15", # 121 IO_L46N_FOE_B_M1DQ3_1
150 "M13", # 122 IO_L46P_FCS_B_M1DQS2_1
151 "L12", # 123 IO_L40N_GCLK10_M1A6_1
152 "K12", # 124 IO_L40P_GCLK11_M1A5_1
153 "K11", # 125 IO_L38N_A4_M1CLKN_1
154 "K10", # 126 IO_L38P_A5_M1CLK_1
155 "J13", # 127 IO_L36N_A8_M1BA1_1
156 "J11", # 128 IO_L36P_A9_M1BA0_1
157 "None", # 129 GND
158 "G13", # 130 IO_L34N_A12_M1BA2_1_NOTLX4
159 "H12", # 131 IO_L34P_A13_M1WE_1_NOTLX4
160 "H11", # 132 IO_L32N_A16_M1A9_1_NOTLX4
161 "H10", # 133 IO_L32P_A17_M1A8_1_NOTLX4
162 "F12", # 134 IO_L31N_A18_M1A12_1_NOTLX4
163 "F11", # 135 IO_L31P_A19_M1CKE_1_NOTLX4
164 "G12", # 136 IO_L30N_A20_M1A11_1_NOTLX4
165 "G11", # 137 IO_L30P_A21_M1RESET_1_NOTLX4
166 "None", # 138 GND
167 "None", # 139 FPGA_BANK3_POWER
168 "None") # 140 FPGA_BANK3_POWER
169 ]
170
171
172 class Platform(XilinxPlatform):
173 default_clk_name = "clk3"
174 default_clk_period = 10.526
175
176 def __init__(self):
177 XilinxPlatform.__init__(self, "xc6slx9-2csg225", _ios, _connectors)