migen/build/platforms/papilio_pro.py

   1 from migen.build.generic_platform import *
   2 from migen.build.xilinx import XilinxPlatform
   3 from migen.build.xilinx.programmer import XC3SProg
   4
   5
   6 _io = [
   7     ("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
   8
   9     ("clk32", 0, Pins("P94"), IOStandard("LVCMOS33")),
  10
  11     ("serial", 0,
  12         Subsignal("tx", Pins("P105"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")),
  13         Subsignal("rx", Pins("P101"), IOStandard("LVCMOS33"), Misc("PULLUP"))
  14     ),
  15
  16     ("spiflash", 0,
  17         Subsignal("cs_n", Pins("P38")),
  18         Subsignal("clk", Pins("P70")),
  19         Subsignal("mosi", Pins("P64")),
  20         Subsignal("miso", Pins("P65"), Misc("PULLUP")),
  21         IOStandard("LVCMOS33"), Misc("SLEW=FAST")
  22     ),
  23     ("spiflash2x", 0,
  24         Subsignal("cs_n", Pins("P38")),
  25         Subsignal("clk", Pins("P70")),
  26         Subsignal("dq", Pins("P64", "P65")),
  27         IOStandard("LVCMOS33"), Misc("SLEW=FAST")
  28     ),
  29
  30     ("sdram_clock", 0, Pins("P32"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
  31     ("sdram", 0,
  32         Subsignal("a", Pins("P140 P139 P138 P137 P46 P45 P44",
  33           "P43 P41 P40 P141 P35 P34")),
  34         Subsignal("ba", Pins("P143 P142")),
  35         Subsignal("cs_n", Pins("P1")),
  36         Subsignal("cke", Pins("P33")),
  37         Subsignal("ras_n", Pins("P2")),
  38         Subsignal("cas_n", Pins("P5")),
  39         Subsignal("we_n", Pins("P6")),
  40         Subsignal("dq", Pins("P9 P10 P11 P12 P14 P15 P16 P8 P21 P22 P23 P24 P26 P27 P29 P30")),
  41         Subsignal("dm", Pins("P7 P17")),
  42         IOStandard("LVCMOS33"), Misc("SLEW=FAST")
  43     )
  44 ]
  45
  46 _connectors = [
  47     ("A", "P48 P51 P56 P58 P61 P66 P67 P75 P79 P81 P83 P85 P88 P93 P98 P100"),
  48     ("B", "P99 P97 P92 P87 P84 P82 P80 P78 P74 P95 P62 P59 P57 P55 P50 P47"),
  49     ("C", "P114 P115 P116 P117 P118 P119 P120 P121 P123 P124 P126 P127 P131 P132 P133 P134")
  50 ]
  51
  52
  53 class Platform(XilinxPlatform):
  54     identifier = 0x5050
  55     default_clk_name = "clk32"
  56     default_clk_period = 31.25
  57
  58     def __init__(self):
  59         XilinxPlatform.__init__(self, "xc6slx9-tqg144-2", _io, _connectors)
  60
  61     def create_programmer(self):
  62         return XC3SProg("papilio", "bscan_spi_lx9_papilio.bit")