migen/build/platforms/rhino.py

   1 from migen.build.generic_platform import *
   2 from migen.build.xilinx import XilinxPlatform
   3
   4
   5 _io = [
   6     ("user_led", 0, Pins("Y3")),
   7     ("user_led", 1, Pins("Y1")),
   8     ("user_led", 2, Pins("W2")),
   9     ("user_led", 3, Pins("W1")),
  10     ("user_led", 4, Pins("V3")),
  11     ("user_led", 5, Pins("V1")),
  12     ("user_led", 6, Pins("U2")),
  13     ("user_led", 7, Pins("U1")),
  14
  15     ("clk100", 0,
  16         Subsignal("p", Pins("B14"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")),
  17         Subsignal("n", Pins("A14"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE"))
  18     ),
  19
  20     ("gpio", 0, Pins("R8")),
  21
  22     ("gpmc", 0,
  23         Subsignal("clk", Pins("R26")),
  24         Subsignal("a", Pins("N17 N18 L23 L24 N19 N20 N21 N22 P17 P19")),
  25         Subsignal("d", Pins("N23 N24 R18 R19 P21 P22 R20 R21 P24 P26 R23 R24 T22 T23 U23 R25")),
  26         Subsignal("we_n", Pins("W26")),
  27         Subsignal("oe_n", Pins("AA25")),
  28         Subsignal("ale_n", Pins("AA26")),
  29         Subsignal("wait", Pins("AD26")),  # WAIT1/BUSY0
  30         IOStandard("LVCMOS33")),
  31     # Warning: CS are numbered 1-7 on ARM side and 0-6 on FPGA side.
  32     # Numbers here are given on the FPGA side.
  33     ("gpmc_ce_n", 0, Pins("V23"), IOStandard("LVCMOS33")),  # nCS0
  34     ("gpmc_ce_n", 1, Pins("U25"), IOStandard("LVCMOS33")),  # nCS1
  35     ("gpmc_ce_n", 2, Pins("W25"), IOStandard("LVCMOS33")),  # nCS6
  36     ("gpmc_dmareq_n", 0, Pins("T24"), IOStandard("LVCMOS33")),  # nCS2
  37     ("gpmc_dmareq_n", 1, Pins("T26"), IOStandard("LVCMOS33")),  # nCS3
  38     ("gpmc_dmareq_n", 2, Pins("V24"), IOStandard("LVCMOS33")),  # nCS4
  39     ("gpmc_dmareq_n", 3, Pins("V26"), IOStandard("LVCMOS33")),  # nCS5
  40
  41     # FMC150
  42     ("fmc150_ctrl", 0,
  43         Subsignal("spi_sclk", Pins("AE5")),
  44         Subsignal("spi_data", Pins("AF5")),
  45
  46         Subsignal("adc_sdo", Pins("U13")),
  47         Subsignal("adc_en_n", Pins("AA15")),
  48         Subsignal("adc_reset", Pins("V13")),
  49
  50         Subsignal("cdce_sdo", Pins("AA8")),
  51         Subsignal("cdce_en_n", Pins("Y9")),
  52         Subsignal("cdce_reset_n", Pins("AB7")),
  53         Subsignal("cdce_pd_n", Pins("AC6")),
  54         Subsignal("cdce_pll_status", Pins("W7")),
  55         Subsignal("cdce_ref_en", Pins("W8")),
  56
  57         Subsignal("dac_sdo", Pins("W9")),
  58         Subsignal("dac_en_n", Pins("W10")),
  59
  60         Subsignal("mon_sdo", Pins("AC5")),
  61         Subsignal("mon_en_n", Pins("AD6")),
  62         Subsignal("mon_reset_n", Pins("AF6")),
  63         Subsignal("mon_int_n", Pins("AD5")),
  64
  65         Subsignal("pg_c2m", Pins("AA23"), IOStandard("LVCMOS33"))
  66     ),
  67     ("ti_dac", 0,  # DAC3283
  68         Subsignal("dat_p", Pins("AA10 AA9 V11 Y11 W14 Y12 AD14 AE13"), IOStandard("LVDS_25")),
  69         Subsignal("dat_n", Pins("AB11 AB9 V10 AA11 Y13 AA12 AF14 AF13"), IOStandard("LVDS_25")),
  70         Subsignal("frame_p", Pins("AB13"), IOStandard("LVDS_25")),
  71         Subsignal("frame_n", Pins("AA13"), IOStandard("LVDS_25")),
  72         Subsignal("txenable", Pins("AB15"), IOStandard("LVCMOS25"))
  73     ),
  74     ("ti_adc", 0,  # ADS62P49
  75         Subsignal("dat_a_p", Pins("AB14 Y21 W20 AB22 V18 W17 AA21")),
  76         Subsignal("dat_a_n", Pins("AC14 AA22 Y20 AC22 W19 W18 AB21")),
  77         Subsignal("dat_b_p", Pins("Y17 U15 AA19 W16 AA18 Y15 V14")),
  78         Subsignal("dat_b_n", Pins("AA17 V16 AB19 Y16 AB17 AA16 V15")),
  79         IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
  80     ),
  81     ("fmc150_clocks", 0,
  82         Subsignal("dac_clk_p", Pins("V12"), IOStandard("LVDS_25")),
  83         Subsignal("dac_clk_n", Pins("W12"), IOStandard("LVDS_25")),
  84         Subsignal("adc_clk_p", Pins("AE15"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")),
  85         Subsignal("adc_clk_n", Pins("AF15"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")),
  86         Subsignal("clk_to_fpga", Pins("W24"), IOStandard("LVCMOS25"))
  87     ),
  88
  89     ("fmc150_ext_trigger", 0, Pins("U26")),
  90
  91     # Vermeer radar testbed
  92     # Switch controller
  93     ("pca9555", 0,
  94         Subsignal("sda", Pins("C13")),
  95         Subsignal("scl", Pins("G8")),
  96         IOStandard("LVCMOS33")
  97     ),
  98     # TX path
  99     ("pe43602", 0,
 100         Subsignal("d", Pins("H8")),
 101         Subsignal("clk", Pins("B3")),
 102         Subsignal("le", Pins("F7")),
 103         IOStandard("LVCMOS33")
 104     ),
 105     ("rfmd2081", 0,
 106         Subsignal("enx", Pins("E5")),
 107         Subsignal("sclk", Pins("G6")),
 108         Subsignal("sdata", Pins("F5")),
 109         Subsignal("locked", Pins("E6")),
 110         IOStandard("LVCMOS33")
 111     ),
 112     # RX path
 113     ("lmh6521", 0,
 114         Subsignal("scsb", Pins("C5")),
 115         Subsignal("sclk", Pins("G10")),
 116         Subsignal("sdi", Pins("D5")),
 117         Subsignal("sdo", Pins("F9")),
 118         IOStandard("LVCMOS33")
 119     ),
 120     ("lmh6521", 1,
 121         Subsignal("scsb", Pins("E10")),
 122         Subsignal("sclk", Pins("A4")),
 123         Subsignal("sdi", Pins("B4")),
 124         Subsignal("sdo", Pins("H10")),
 125         IOStandard("LVCMOS33")
 126     ),
 127     ("rffc5071", 0,
 128         Subsignal("enx", Pins("A2")),
 129         Subsignal("sclk", Pins("G9")),
 130         Subsignal("sdata", Pins("H9")),
 131         Subsignal("locked", Pins("A3")),
 132         IOStandard("LVCMOS33")
 133     )
 134 ]
 135
 136
 137 class Platform(XilinxPlatform):
 138     default_clk_name = "clk100"
 139     default_clk_period = 10
 140
 141     def __init__(self):
 142         XilinxPlatform.__init__(self, "xc6slx150t-fgg676-3", _io)