0e4a40d1be49e7ca8780247062fa9cd62c507eb2
1 from migen
.build
.generic_platform
import *
2 from migen
.build
.sim
import SimPlatform
7 Pins
.__init
__(self
, "s "*n
)
10 ("sys_clk", 0, SimPins(1)),
11 ("sys_rst", 0, SimPins(1)),
13 Subsignal("source_stb", SimPins(1)),
14 Subsignal("source_ack", SimPins(1)),
15 Subsignal("source_data", SimPins(8)),
17 Subsignal("sink_stb", SimPins(1)),
18 Subsignal("sink_ack", SimPins(1)),
19 Subsignal("sink_data", SimPins(8)),
22 Subsignal("none", SimPins(1)),
25 Subsignal("source_stb", SimPins(1)),
26 Subsignal("source_ack", SimPins(1)),
27 Subsignal("source_data", SimPins(8)),
29 Subsignal("sink_stb", SimPins(1)),
30 Subsignal("sink_ack", SimPins(1)),
31 Subsignal("sink_data", SimPins(8)),
36 class Platform(SimPlatform
):
38 default_clk_name
= "sys_clk"
39 default_clk_period
= 1000 # on modern computers simulate at ~ 1MHz
42 SimPlatform
.__init
__(self
, "SIM", _io
)
44 def do_finalize(self
, fragment
):