migen/build/xilinx/vivado.py

   1 # This file is Copyright (c) 2014 Florent Kermarrec <florent@enjoy-digital.fr>
   2 # License: BSD
   3
   4 import os
   5 import subprocess
   6 import sys
   7
   8 from migen.fhdl.structure import _Fragment
   9 from migen.build.generic_platform import *
  10 from migen.build import tools
  11 from migen.build.xilinx import common
  12
  13
  14 def _format_constraint(c):
  15     if isinstance(c, Pins):
  16         return "set_property LOC " + c.identifiers[0]
  17     elif isinstance(c, IOStandard):
  18         return "set_property IOSTANDARD " + c.name
  19     elif isinstance(c, Drive):
  20         return "set_property DRIVE " + str(c.strength)
  21     elif isinstance(c, Misc):
  22         return "set_property " + c.misc.replace("=", " ")
  23     else:
  24         raise ValueError("unknown constraint {}".format(c))
  25
  26
  27 def _format_xdc(signame, resname, *constraints):
  28     fmt_c = [_format_constraint(c) for c in constraints]
  29     fmt_r = resname[0] + ":" + str(resname[1])
  30     if resname[2] is not None:
  31         fmt_r += "." + resname[2]
  32     r = " ## {}\n".format(fmt_r)
  33     for c in fmt_c:
  34         r += c + " [get_ports " + signame + "]\n"
  35     return r
  36
  37
  38 def _build_xdc(named_sc, named_pc):
  39     r = ""
  40     for sig, pins, others, resname in named_sc:
  41         if len(pins) > 1:
  42             for i, p in enumerate(pins):
  43                 r += _format_xdc(sig + "[" + str(i) + "]", resname, Pins(p), *others)
  44         elif pins:
  45             r += _format_xdc(sig, resname, Pins(pins[0]), *others)
  46         else:
  47             r += _format_xdc(sig, resname, *others)
  48     if named_pc:
  49         r += "\n" + "\n\n".join(named_pc)
  50     return r
  51
  52
  53 def _run_vivado(build_name, vivado_path, source, ver=None):
  54     if sys.platform == "win32" or sys.platform == "cygwin":
  55         build_script_contents = "REM Autogenerated by Migen\n"
  56         build_script_contents += "vivado -mode batch -source " + build_name + ".tcl\n"
  57         build_script_file = "build_" + build_name + ".bat"
  58         tools.write_to_file(build_script_file, build_script_contents)
  59         r = subprocess.call([build_script_file])
  60     else:
  61         build_script_contents = "# Autogenerated by Migen\nset -e\n"
  62         settings = common.settings(vivado_path, ver)
  63         build_script_contents += "source " + settings + "\n"
  64         build_script_contents += "vivado -mode batch -source " + build_name + ".tcl\n"
  65         build_script_file = "build_" + build_name + ".sh"
  66         tools.write_to_file(build_script_file, build_script_contents)
  67         r = subprocess.call(["bash", build_script_file])
  68
  69     if r != 0:
  70         raise OSError("Subprocess failed")
  71
  72
  73 class XilinxVivadoToolchain:
  74     def __init__(self):
  75         self.bitstream_commands = []
  76         self.additional_commands = []
  77         self.pre_synthesis_commands = []
  78         self.with_phys_opt = False
  79
  80     def _build_batch(self, platform, sources, build_name):
  81         tcl = []
  82         for filename, language, library in sources:
  83             filename_tcl = "{" + filename + "}"
  84             tcl.append("add_files " + filename_tcl)
  85             tcl.append("set_property library {} [get_files {}]"
  86                        .format(library, filename_tcl))
  87
  88         tcl.append("read_xdc {}.xdc".format(build_name))
  89         tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
  90         tcl.append("synth_design -top top -part {} -include_dirs {{{}}}".format(platform.device, " ".join(platform.verilog_include_paths)))
  91         tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name))
  92         tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name))
  93         tcl.append("place_design")
  94         if self.with_phys_opt:
  95             tcl.append("phys_opt_design -directive AddRetime")
  96         tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_place.rpt".format(build_name))
  97         tcl.append("report_utilization -file {}_utilization_place.rpt".format(build_name))
  98         tcl.append("report_io -file {}_io.rpt".format(build_name))
  99         tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(build_name))
 100         tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name))
 101         tcl.append("route_design")
 102         tcl.append("report_route_status -file {}_route_status.rpt".format(build_name))
 103         tcl.append("report_drc -file {}_drc.rpt".format(build_name))
 104         tcl.append("report_timing_summary -max_paths 10 -file {}_timing.rpt".format(build_name))
 105         tcl.append("report_power -file {}_power.rpt".format(build_name))
 106         for bitstream_command in self.bitstream_commands:
 107             tcl.append(bitstream_command.format(build_name=build_name))
 108         tcl.append("write_bitstream -force {}.bit ".format(build_name))
 109         for additional_command in self.additional_commands:
 110             tcl.append(additional_command.format(build_name=build_name))
 111         tcl.append("quit")
 112         tools.write_to_file(build_name + ".tcl", "\n".join(tcl))
 113
 114     def build(self, platform, fragment, build_dir="build", build_name="top",
 115             toolchain_path="/opt/Xilinx/Vivado", source=True, run=True):
 116         tools.mkdir_noerror(build_dir)
 117         os.chdir(build_dir)
 118
 119         if not isinstance(fragment, _Fragment):
 120             fragment = fragment.get_fragment()
 121         platform.finalize(fragment)
 122         v_output = platform.get_verilog(fragment)
 123         named_sc, named_pc = platform.resolve_signals(v_output.ns)
 124         v_file = build_name + ".v"
 125         v_output.write(v_file)
 126         sources = platform.sources | {(v_file, "verilog", "work")}
 127         self._build_batch(platform, sources, build_name)
 128         tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
 129         if run:
 130             _run_vivado(build_name, toolchain_path, source)
 131
 132         os.chdir("..")
 133
 134         return v_output.ns
 135
 136     def add_period_constraint(self, platform, clk, period):
 137         platform.add_platform_command("""create_clock -name {clk} -period """ + \
 138             str(period) + """ [get_ports {clk}]""", clk=clk)