6dfc9c4ede52c83238e296427887df0757b5f496
[litex.git] / migen / test / test_fifo.py
1 import unittest
2 from itertools import count
3
4 from migen import *
5 from migen.genlib.fifo import SyncFIFO
6
7 from migen.test.support import SimCase
8
9
10 class SyncFIFOCase(SimCase, unittest.TestCase):
11 class TestBench(Module):
12 def __init__(self):
13 self.submodules.dut = SyncFIFO(64, 2)
14
15 self.sync += [
16 If(self.dut.we & self.dut.writable,
17 self.dut.din[:32].eq(self.dut.din[:32] + 1),
18 self.dut.din[32:].eq(self.dut.din[32:] + 2)
19 )
20 ]
21
22 def test_run_sequence(self):
23 seq = list(range(20))
24 def gen():
25 for cycle in count():
26 # fire re and we at "random"
27 yield self.tb.dut.we.eq(cycle % 2 == 0)
28 yield self.tb.dut.re.eq(cycle % 3 == 0)
29 # the output if valid must be correct
30 if (yield self.tb.dut.readable) and (yield self.tb.dut.re):
31 try:
32 i = seq.pop(0)
33 except IndexError:
34 break
35 self.assertEqual((yield self.tb.dut.dout[:32]), i)
36 self.assertEqual((yield self.tb.dut.dout[32:]), i*2)
37 yield
38 self.run_with(gen())
39
40 def test_replace(self):
41 seq = [x for x in range(20) if x % 5]
42 def gen():
43 for cycle in count():
44 yield self.tb.dut.we.eq(cycle % 2 == 0)
45 yield self.tb.dut.re.eq(cycle % 7 == 0)
46 yield self.tb.dut.replace.eq(
47 (yield self.tb.dut.din[:32]) % 5 == 1)
48 if (yield self.tb.dut.readable) and (yield self.tb.dut.re):
49 try:
50 i = seq.pop(0)
51 except IndexError:
52 break
53 self.assertEqual((yield self.tb.dut.dout[:32]), i)
54 self.assertEqual((yield self.tb.dut.dout[32:]), i*2)
55 yield
56 self.run_with(gen())