6dfc9c4ede52c83238e296427887df0757b5f496
2 from itertools
import count
5 from migen
.genlib
.fifo
import SyncFIFO
7 from migen
.test
.support
import SimCase
10 class SyncFIFOCase(SimCase
, unittest
.TestCase
):
11 class TestBench(Module
):
13 self
.submodules
.dut
= SyncFIFO(64, 2)
16 If(self
.dut
.we
& self
.dut
.writable
,
17 self
.dut
.din
[:32].eq(self
.dut
.din
[:32] + 1),
18 self
.dut
.din
[32:].eq(self
.dut
.din
[32:] + 2)
22 def test_run_sequence(self
):
26 # fire re and we at "random"
27 yield self
.tb
.dut
.we
.eq(cycle
% 2 == 0)
28 yield self
.tb
.dut
.re
.eq(cycle
% 3 == 0)
29 # the output if valid must be correct
30 if (yield self
.tb
.dut
.readable
) and (yield self
.tb
.dut
.re
):
35 self
.assertEqual((yield self
.tb
.dut
.dout
[:32]), i
)
36 self
.assertEqual((yield self
.tb
.dut
.dout
[32:]), i
*2)
40 def test_replace(self
):
41 seq
= [x
for x
in range(20) if x
% 5]
44 yield self
.tb
.dut
.we
.eq(cycle
% 2 == 0)
45 yield self
.tb
.dut
.re
.eq(cycle
% 7 == 0)
46 yield self
.tb
.dut
.replace
.eq(
47 (yield self
.tb
.dut
.din
[:32]) % 5 == 1)
48 if (yield self
.tb
.dut
.readable
) and (yield self
.tb
.dut
.re
):
53 self
.assertEqual((yield self
.tb
.dut
.dout
[:32]), i
)
54 self
.assertEqual((yield self
.tb
.dut
.dout
[32:]), i
*2)