3b18412e01e3540a91097be576863c0678476cec
[litex.git] / milkymist / asmicon / bankmachine.py
1 from migen.fhdl.structure import *
2 from migen.bus.asmibus import *
3 from migen.corelogic.roundrobin import *
4 from migen.corelogic.fsm import FSM
5 from migen.corelogic.misc import optree
6
7 from milkymist.asmicon.multiplexer import *
8
9 # Row:Bank:Col address mapping
10 class _AddressSlicer:
11 def __init__(self, geom_settings, address_align):
12 self.geom_settings = geom_settings
13 self.address_align = address_align
14
15 self._b1 = self.geom_settings.col_a - self.address_align
16 self._b2 = self._b1 + self.geom_settings.bank_a
17
18 def row(self, address):
19 if isinstance(address, int):
20 return address >> self._b2
21 else:
22 return address[self._b2:]
23
24 def bank(self, address):
25 if isinstance(address, int):
26 return (address & (2**self._b2 - 1)) >> self._b1
27 else:
28 return address[self._b1:self._b2]
29
30 def col(self, address):
31 if isinstance(address, int):
32 return (address & (2**self._b1 - 1)) << self.address_align
33 else:
34 return Cat(Constant(0, BV(self.address_align)), address[:self._b1])
35
36 class _Selector:
37 def __init__(self, slicer, bankn, slots):
38 self.slicer = slicer
39 self.bankn = bankn
40 self.slots = slots
41
42 self.nslots = len(self.slots)
43 self.stb = Signal()
44 self.ack = Signal()
45 self.tag = Signal(BV(bits_for(self.nslots-1)))
46 self.adr = Signal(self.slots[0].adr.bv)
47 self.we = Signal()
48
49 def get_fragment(self):
50 comb = []
51 sync = []
52
53 # List outstanding requests for our bank
54 outstandings = []
55 for slot in self.slots:
56 outstanding = Signal()
57 comb.append(outstanding.eq(
58 (self.slicer.bank(slot.adr) == self.bankn) & \
59 (slot.state == SLOT_PENDING)
60 ))
61 outstandings.append(outstanding)
62
63 # Row tracking
64 openrow_r = Signal(BV(self.slicer.geom_settings.row_a))
65 openrow_n = Signal(BV(self.slicer.geom_settings.row_a))
66 openrow = Signal(BV(self.slicer.geom_settings.row_a))
67 comb += [
68 openrow_n.eq(self.slicer.row(self.adr)),
69 If(self.stb,
70 openrow.eq(openrow_n)
71 ).Else(
72 openrow.eq(openrow_r)
73 )
74 ]
75 sync += [
76 If(self.stb & self.ack,
77 openrow_r.eq(openrow_n)
78 )
79 ]
80 hits = []
81 for slot, os in zip(self.slots, outstandings):
82 hit = Signal()
83 comb.append(hit.eq((self.slicer.row(slot.adr) == openrow) & os))
84 hits.append(hit)
85
86 # Determine best request
87 rr = RoundRobin(self.nslots, SP_CE)
88 has_hit = Signal()
89 comb.append(has_hit.eq(optree("|", hits)))
90
91 best_hit = [rr.request[i].eq(hit)
92 for i, hit in enumerate(hits)]
93 best_fallback = [rr.request[i].eq(os)
94 for i, os in enumerate(outstandings)]
95 select_stmt = If(has_hit,
96 *best_hit
97 ).Else(
98 *best_fallback
99 )
100
101 if self.slots[0].time:
102 # Implement anti-starvation timer
103 matures = []
104 for slot, os in zip(self.slots, outstandings):
105 mature = Signal()
106 comb.append(mature.eq(slot.mature & os))
107 matures.append(mature)
108 has_mature = Signal()
109 comb.append(has_mature.eq(optree("|", matures)))
110 best_mature = [rr.request[i].eq(mature)
111 for i, mature in enumerate(matures)]
112 select_stmt = If(has_mature, *best_mature).Else(select_stmt)
113 comb.append(select_stmt)
114
115 # Multiplex
116 state = Signal(BV(2))
117 comb += [
118 state.eq(Array(slot.state for slot in self.slots)[rr.grant]),
119 self.adr.eq(Array(slot.adr for slot in self.slots)[rr.grant]),
120 self.we.eq(Array(slot.we for slot in self.slots)[rr.grant]),
121 self.stb.eq(
122 (self.slicer.bank(self.adr) == self.bankn) \
123 & (state == SLOT_PENDING)),
124 rr.ce.eq(self.ack),
125 self.tag.eq(rr.grant)
126 ]
127 comb += [If((rr.grant == i) & self.stb & self.ack, slot.process.eq(1))
128 for i, slot in enumerate(self.slots)]
129
130 return Fragment(comb, sync) + rr.get_fragment()
131
132 class _Buffer:
133 def __init__(self, source):
134 self.source = source
135
136 self.stb = Signal()
137 self.ack = Signal()
138 self.tag = Signal(self.source.tag.bv)
139 self.adr = Signal(self.source.adr.bv)
140 self.we = Signal()
141
142 def get_fragment(self):
143 en = Signal()
144 comb = [
145 en.eq(self.ack | ~self.stb),
146 self.source.ack.eq(en)
147 ]
148 sync = [
149 If(en,
150 self.stb.eq(self.source.stb),
151 self.tag.eq(self.source.tag),
152 self.adr.eq(self.source.adr),
153 self.we.eq(self.source.we)
154 )
155 ]
156 return Fragment(comb, sync)
157
158 class BankMachine:
159 def __init__(self, geom_settings, timing_settings, address_align, bankn, slots):
160 self.geom_settings = geom_settings
161 self.timing_settings = timing_settings
162 self.address_align = address_align
163 self.bankn = bankn
164 self.slots = slots
165
166 self.refresh_req = Signal()
167 self.refresh_gnt = Signal()
168 self.cmd = CommandRequestRW(geom_settings.mux_a, geom_settings.bank_a,
169 bits_for(len(slots)-1))
170
171 def get_fragment(self):
172 comb = []
173 sync = []
174
175 # Sub components
176 slicer = _AddressSlicer(self.geom_settings, self.address_align)
177 selector = _Selector(slicer, self.bankn, self.slots)
178 buf = _Buffer(selector)
179
180 # Row tracking
181 has_openrow = Signal()
182 openrow = Signal(BV(self.geom_settings.row_a))
183 hit = Signal()
184 comb.append(hit.eq(openrow == slicer.row(buf.adr)))
185 track_open = Signal()
186 track_close = Signal()
187 sync += [
188 If(track_open,
189 has_openrow.eq(1),
190 openrow.eq(slicer.row(buf.adr))
191 ),
192 If(track_close,
193 has_openrow.eq(0)
194 )
195 ]
196
197 # Address generation
198 s_row_adr = Signal()
199 comb += [
200 self.cmd.ba.eq(self.bankn),
201 If(s_row_adr,
202 self.cmd.a.eq(slicer.row(buf.adr))
203 ).Else(
204 self.cmd.a.eq(slicer.col(buf.adr))
205 )
206 ]
207
208 comb.append(self.cmd.tag.eq(buf.tag))
209
210 # Control and command generation FSM
211 fsm = FSM("REGULAR", "PRECHARGE", "ACTIVATE", "REFRESH", delayed_enters=[
212 ("TRP", "ACTIVATE", self.timing_settings.tRP-1),
213 ("TRCD", "REGULAR", self.timing_settings.tRCD-1)
214 ])
215 fsm.act(fsm.REGULAR,
216 If(self.refresh_req,
217 fsm.next_state(fsm.REFRESH)
218 ).Elif(buf.stb,
219 If(has_openrow,
220 If(hit,
221 self.cmd.stb.eq(1),
222 buf.ack.eq(self.cmd.ack),
223 self.cmd.is_read.eq(~buf.we),
224 self.cmd.is_write.eq(buf.we),
225 self.cmd.cas_n.eq(0),
226 self.cmd.we_n.eq(~buf.we)
227 ).Else(
228 fsm.next_state(fsm.PRECHARGE)
229 )
230 ).Else(
231 fsm.next_state(fsm.ACTIVATE)
232 )
233 )
234 )
235 fsm.act(fsm.PRECHARGE,
236 # Notes:
237 # 1. we are presenting the column address, A10 is always low
238 # 2. since we always go to the ACTIVATE state, we do not need
239 # to assert track_close.
240 self.cmd.stb.eq(1),
241 If(self.cmd.ack, fsm.next_state(fsm.TRP)),
242 self.cmd.ras_n.eq(0),
243 self.cmd.we_n.eq(0)
244 )
245 fsm.act(fsm.ACTIVATE,
246 s_row_adr.eq(1),
247 track_open.eq(1),
248 self.cmd.stb.eq(1),
249 If(self.cmd.ack, fsm.next_state(fsm.TRCD)),
250 self.cmd.ras_n.eq(0)
251 )
252 fsm.act(fsm.REFRESH,
253 self.refresh_gnt.eq(1),
254 track_close.eq(1),
255 If(~self.refresh_req, fsm.next_state(fsm.REGULAR))
256 )
257
258 return Fragment(comb, sync) + \
259 selector.get_fragment() + \
260 buf.get_fragment() + \
261 fsm.get_fragment()