2 // yosys -- Yosys Open SYnthesis Suite
4 // Copyright (C) 2018 Serge Bazanski <q3k@symbioticeda.com>
6 // Permission to use, copy, modify, and/or distribute this software for any
7 // purpose with or without fee is hereby granted, provided that the above
8 // copyright notice and this permission notice appear in all copies.
10 // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 /// Protobuf definition of Yosys RTLIL dump/restore format for RTL designs.
27 DIRECTION_INVALID = 0;
33 // A freeform parameter/attribute value.
41 // A signal in the design - either a unique identifier for one, or a constant
42 // driver (low or high).
44 // A constant signal driver in the design.
46 CONSTANT_DRIVER_INVALID = 0;
47 CONSTANT_DRIVER_LOW = 1;
48 CONSTANT_DRIVER_HIGH = 2;
49 CONSTANT_DRIVER_Z = 3;
50 CONSTANT_DRIVER_X = 4;
53 // Signal uniquely identified by ID number.
56 ConstantDriver constant = 2;
60 // A vector of signals.
62 repeated Signal signal = 1;
67 // Freeform attributes.
68 map<string, Parameter> attribute = 1;
70 // Named ports in this module.
72 Direction direction = 1;
75 map<string, Port> port = 2;
77 // Named cells in this module.
79 // Set to true when the name of this cell is automatically created and
80 // likely not of interest for a regular user.
83 // Set if this module has an AIG model available.
85 // Freeform parameters.
86 map<string, Parameter> parameter = 4;
87 // Freeform attributes.
88 map<string, Parameter> attribute = 5;
90 /// Ports of the cell.
91 // Direction of the port, if interface is known.
92 map<string, Direction> port_direction = 6;
93 // Connection of named port to signal(s).
94 map<string, BitVector> connection = 7;
96 map<string, Cell> cell = 3;
98 // Nets in this module.
100 // Set to true when the name of this net is automatically created and
101 // likely not of interest for a regular user.
103 // Signal(s) that make up this net.
105 // Freeform attributes.
106 map<string, Parameter> attributes = 3;
108 repeated Netname netname = 4;
111 // And-Inverter-Graph model.
114 // Type of AIG node - or, what its' value is.
117 // The node's value is the value of the specified input port bit.
119 // The node's value is the inverted value of the specified input
122 // The node's value is the ANDed value of specified nodes.
124 // The node's value is the NANDed value of specified nodes.
126 // The node's value is a constant 1.
128 // The node's value is a constant 0.
136 // Bit index in port.
140 // Node index of left side of operation.
142 // Node index of right side of operation.
146 // Set for PORT, NPORT
148 // Set for AND, NAND.
152 // Set when the node drives given output port(s).
156 // Bit index in port.
159 repeated OutPort out_port = 4;
162 // List of AIG nodes - each is explicitely numbered by its' index in this
164 repeated Node node = 1;
167 // A Yosys design netlist dumped from RTLIL.
169 // Human-readable freeform 'remark' string.
171 // List of named modules in design.
172 map<string, Module> modules = 2;
173 // List of named AIG models in design (if AIG export enabled).
174 map<string, Model> models = 3;