misoclib/dvisampler/clocking.py

   1 from migen.fhdl.std import *
   2 from migen.genlib.cdc import MultiReg
   3 from migen.bank.description import *
   4
   5 class Clocking(Module, AutoCSR):
   6         def __init__(self, pads):
   7                 self._r_pll_reset = CSRStorage(reset=1)
   8                 self._r_locked = CSRStatus()
   9
  10                 # DRP
  11                 self._r_pll_adr = CSRStorage(5)
  12                 self._r_pll_dat_r = CSRStatus(16)
  13                 self._r_pll_dat_w = CSRStorage(16)
  14                 self._r_pll_read = CSR()
  15                 self._r_pll_write = CSR()
  16                 self._r_pll_drdy = CSRStatus()
  17
  18                 self.locked = Signal()
  19                 self.serdesstrobe = Signal()
  20                 self.clock_domains._cd_pix = ClockDomain()
  21                 self.clock_domains._cd_pix2x = ClockDomain()
  22                 self.clock_domains._cd_pix10x = ClockDomain(reset_less=True)
  23
  24                 ###
  25
  26                 clk_se = Signal()
  27                 self.specials += Instance("IBUFDS", i_I=pads.clk_p, i_IB=pads.clk_n, o_O=clk_se)
  28
  29                 clkfbout = Signal()
  30                 pll_locked = Signal()
  31                 pll_clk0 = Signal()
  32                 pll_clk1 = Signal()
  33                 pll_clk2 = Signal()
  34                 pll_drdy = Signal()
  35                 self.sync += If(self._r_pll_read.re | self._r_pll_write.re,
  36                         self._r_pll_drdy.status.eq(0)
  37                 ).Elif(pll_drdy,
  38                         self._r_pll_drdy.status.eq(1)
  39                 )
  40                 self.specials += Instance("PLL_ADV",
  41                         p_CLKFBOUT_MULT=10,
  42                         p_CLKOUT0_DIVIDE=1,  # pix10x
  43                         p_CLKOUT1_DIVIDE=5,  # pix2x
  44                         p_CLKOUT2_DIVIDE=10, # pix
  45                         p_COMPENSATION="INTERNAL",
  46
  47                         i_CLKINSEL=1,
  48                         i_CLKIN1=clk_se,
  49                         o_CLKOUT0=pll_clk0, o_CLKOUT1=pll_clk1, o_CLKOUT2=pll_clk2,
  50                         o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbout,
  51                         o_LOCKED=pll_locked, i_RST=self._r_pll_reset.storage,
  52
  53                         i_DADDR=self._r_pll_adr.storage,
  54                         o_DO=self._r_pll_dat_r.status,
  55                         i_DI=self._r_pll_dat_w.storage,
  56                         i_DEN=self._r_pll_read.re | self._r_pll_write.re,
  57                         i_DWE=self._r_pll_write.re,
  58                         o_DRDY=pll_drdy,
  59                         i_DCLK=ClockSignal())
  60
  61                 locked_async = Signal()
  62                 self.specials += [
  63                         Instance("BUFPLL", p_DIVIDE=5,
  64                                 i_PLLIN=pll_clk0, i_GCLK=ClockSignal("pix2x"), i_LOCKED=pll_locked,
  65                                 o_IOCLK=self._cd_pix10x.clk, o_LOCK=locked_async, o_SERDESSTROBE=self.serdesstrobe),
  66                         Instance("BUFG", i_I=pll_clk1, o_O=self._cd_pix2x.clk),
  67                         Instance("BUFG", i_I=pll_clk2, o_O=self._cd_pix.clk),
  68                         MultiReg(locked_async, self.locked, "sys")
  69                 ]
  70                 self.comb += self._r_locked.status.eq(self.locked)
  71
  72                 # sychronize pix+pix2x reset
  73                 pix_rst_n = 1
  74                 for i in range(2):
  75                         new_pix_rst_n = Signal()
  76                         self.specials += Instance("FDCE", i_D=pix_rst_n, i_CE=1, i_C=ClockSignal("pix"),
  77                                 i_CLR=~locked_async, o_Q=new_pix_rst_n)
  78                         pix_rst_n = new_pix_rst_n
  79                 self.comb += self._cd_pix.rst.eq(~pix_rst_n), self._cd_pix2x.rst.eq(~pix_rst_n)