misoclib/dvisampler/debug.py

   1 from migen.fhdl.std import *
   2 from migen.genlib.fifo import AsyncFIFO
   3 from migen.genlib.record import layout_len
   4 from migen.bank.description import AutoCSR
   5 from migen.actorlib import structuring, dma_lasmi, spi
   6
   7 from misoclib.dvisampler.edid import EDID
   8 from misoclib.dvisampler.clocking import Clocking
   9 from misoclib.dvisampler.datacapture import DataCapture
  10
  11 class RawDVISampler(Module, AutoCSR):
  12         def __init__(self, pads, asmiport):
  13                 self.submodules.edid = EDID(pads)
  14                 self.submodules.clocking = Clocking(pads)
  15
  16                 invert = False
  17                 try:
  18                         s = getattr(pads, "data0")
  19                 except AttributeError:
  20                         s = getattr(pads, "data0_n")
  21                         invert = True
  22                 self.submodules.data0_cap = DataCapture(8, invert)
  23                 self.comb += [
  24                         self.data0_cap.pad.eq(s),
  25                         self.data0_cap.serdesstrobe.eq(self.clocking.serdesstrobe)
  26                 ]
  27
  28                 fifo = RenameClockDomains(AsyncFIFO(10, 256),
  29                         {"write": "pix", "read": "sys"})
  30                 self.submodules += fifo
  31                 self.comb += [
  32                         fifo.din.eq(self.data0_cap.d),
  33                         fifo.we.eq(1)
  34                 ]
  35
  36                 pack_factor = asmiport.hub.dw//16
  37                 self.submodules.packer = structuring.Pack([("word", 10), ("pad", 6)], pack_factor)
  38                 self.submodules.cast = structuring.Cast(self.packer.source.payload.layout, asmiport.hub.dw)
  39                 self.submodules.dma = spi.DMAWriteController(dma_lasmi.Writer(lasmim), spi.MODE_SINGLE_SHOT)
  40                 self.comb += [
  41                         self.packer.sink.stb.eq(fifo.readable),
  42                         fifo.re.eq(self.packer.sink.ack),
  43                         self.packer.sink.payload.word.eq(fifo.dout),
  44                         self.packer.source.connect_flat(self.cast.sink),
  45                         self.cast.source.connect_flat(self.dma.data)
  46                 ]