2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
9 -- Supports 4-level trees as in arch 3.0B, but not the two-step translation for
10 -- guests under a hypervisor (i.e. there is no gRA -> hRA translation).
17 l_in : in Loadstore1ToMmuType;
18 l_out : out MmuToLoadstore1Type;
20 d_out : out MmuToDcacheType;
21 d_in : in DcacheToMmuType;
23 i_out : out MmuToIcacheType
27 architecture behave of mmu is
29 type state_t is (IDLE,
40 type reg_stage_t is record
41 -- latched request from loadstore1
46 addr : std_ulogic_vector(63 downto 0);
48 prtbl : std_ulogic_vector(63 downto 0);
49 pid : std_ulogic_vector(31 downto 0);
52 pgtbl0 : std_ulogic_vector(63 downto 0);
53 pt0_valid : std_ulogic;
54 pgtbl3 : std_ulogic_vector(63 downto 0);
55 pt3_valid : std_ulogic;
56 shift : unsigned(5 downto 0);
57 mask_size : unsigned(4 downto 0);
58 pgbase : std_ulogic_vector(55 downto 0);
59 pde : std_ulogic_vector(63 downto 0);
62 segerror : std_ulogic;
63 perm_err : std_ulogic;
64 rc_error : std_ulogic;
67 signal r, rin : reg_stage_t;
69 signal addrsh : std_ulogic_vector(15 downto 0);
70 signal mask : std_ulogic_vector(15 downto 0);
71 signal finalmask : std_ulogic_vector(43 downto 0);
74 -- Multiplex internal SPR values back to loadstore1, selected
76 l_out.sprval <= r.prtbl when l_in.sprn(9) = '1' else x"00000000" & r.pid;
80 if rising_edge(clk) then
86 r.prtbl <= (others => '0');
88 if rin.valid = '1' then
89 report "MMU got tlb miss for " & to_hstring(rin.addr);
91 if l_out.done = '1' then
92 report "MMU completing op with invalid=" & std_ulogic'image(l_out.invalid) &
93 " badtree=" & std_ulogic'image(l_out.badtree);
95 if rin.state = RADIX_LOOKUP then
96 report "radix lookup shift=" & integer'image(to_integer(rin.shift)) &
97 " msize=" & integer'image(to_integer(rin.mask_size));
99 if r.state = RADIX_LOOKUP then
100 report "send load addr=" & to_hstring(d_out.addr) &
101 " addrsh=" & to_hstring(addrsh) & " mask=" & to_hstring(mask);
108 -- Shift address bits 61--12 right by 0--47 bits and
109 -- supply the least significant 16 bits of the result.
110 addrshifter: process(all)
111 variable sh1 : std_ulogic_vector(30 downto 0);
112 variable sh2 : std_ulogic_vector(18 downto 0);
113 variable result : std_ulogic_vector(15 downto 0);
115 case r.shift(5 downto 4) is
117 sh1 := r.addr(42 downto 12);
119 sh1 := r.addr(58 downto 28);
121 sh1 := "0000000000000" & r.addr(61 downto 44);
123 case r.shift(3 downto 2) is
125 sh2 := sh1(18 downto 0);
127 sh2 := sh1(22 downto 4);
129 sh2 := sh1(26 downto 8);
131 sh2 := sh1(30 downto 12);
133 case r.shift(1 downto 0) is
135 result := sh2(15 downto 0);
137 result := sh2(16 downto 1);
139 result := sh2(17 downto 2);
141 result := sh2(18 downto 3);
146 -- generate mask for extracting address fields for PTE address generation
147 addrmaskgen: process(all)
148 variable m : std_ulogic_vector(15 downto 0);
150 -- mask_count has to be >= 5
152 for i in 5 to 15 loop
153 if i < to_integer(r.mask_size) then
160 -- generate mask for extracting address bits to go in TLB entry
161 -- in order to support pages > 4kB
162 finalmaskgen: process(all)
163 variable m : std_ulogic_vector(43 downto 0);
165 m := (others => '0');
166 for i in 0 to 43 loop
167 if i < to_integer(r.shift) then
175 variable v : reg_stage_t;
176 variable dcreq : std_ulogic;
177 variable done : std_ulogic;
178 variable tlb_load : std_ulogic;
179 variable itlb_load : std_ulogic;
180 variable tlbie_req : std_ulogic;
181 variable inval_all : std_ulogic;
182 variable prtbl_rd : std_ulogic;
183 variable pt_valid : std_ulogic;
184 variable effpid : std_ulogic_vector(31 downto 0);
185 variable prtable_addr : std_ulogic_vector(63 downto 0);
186 variable rts : unsigned(5 downto 0);
187 variable mbits : unsigned(5 downto 0);
188 variable pgtable_addr : std_ulogic_vector(63 downto 0);
189 variable pte : std_ulogic_vector(63 downto 0);
190 variable tlb_data : std_ulogic_vector(63 downto 0);
191 variable nonzero : std_ulogic;
192 variable pgtbl : std_ulogic_vector(63 downto 0);
193 variable perm_ok : std_ulogic;
194 variable rc_ok : std_ulogic;
195 variable addr : std_ulogic_vector(63 downto 0);
196 variable data : std_ulogic_vector(63 downto 0);
213 -- Radix tree data structures in memory are big-endian,
214 -- so we need to byte-swap them
216 data(i * 8 + 7 downto i * 8) := d_in.data((7 - i) * 8 + 7 downto (7 - i) * 8);
221 if l_in.addr(63) = '0' then
223 pt_valid := r.pt0_valid;
226 pt_valid := r.pt3_valid;
228 -- rts == radix tree size, # address bits being translated
229 rts := unsigned('0' & pgtbl(62 downto 61) & pgtbl(7 downto 5));
230 -- mbits == # address bits to index top level of tree
231 mbits := unsigned('0' & pgtbl(4 downto 0));
232 -- set v.shift to rts so that we can use finalmask for the segment check
234 v.mask_size := mbits(4 downto 0);
235 v.pgbase := pgtbl(55 downto 8) & x"00";
237 if l_in.valid = '1' then
239 v.iside := l_in.iside;
240 v.store := not (l_in.load or l_in.iside);
242 if l_in.tlbie = '1' then
245 -- Invalidate all iTLB/dTLB entries for tlbie with
246 -- RB[IS] != 0 or RB[AP] != 0, or for slbia
247 inval_all := l_in.slbia or l_in.addr(11) or l_in.addr(10) or
248 l_in.addr(7) or l_in.addr(6) or l_in.addr(5);
249 -- The RIC field of the tlbie instruction comes across on the
250 -- sprn bus as bits 2--3. RIC=2 flushes process table caches.
251 if l_in.sprn(3) = '1' then
258 if pt_valid = '0' then
259 -- need to fetch process table entry
260 -- set v.shift so we can use finalmask for generating
261 -- the process table entry address
262 v.shift := unsigned('0' & r.prtbl(4 downto 0));
263 v.state := PROC_TBL_READ;
265 -- Use RPDS = 0 to disable radix tree walks
266 v.state := RADIX_ERROR;
269 v.state := SEGMENT_CHECK;
273 if l_in.mtspr = '1' then
274 -- Move to PID needs to invalidate L1 TLBs and cached
275 -- pgtbl0 value. Move to PRTBL does that plus
276 -- invalidating the cached pgtbl3 value as well.
277 if l_in.sprn(9) = '0' then
278 v.pid := l_in.rs(31 downto 0);
291 if d_in.done = '1' then
296 when PROC_TBL_READ =>
299 v.state := PROC_TBL_WAIT;
301 when PROC_TBL_WAIT =>
302 if d_in.done = '1' then
303 if d_in.err = '0' then
304 if r.addr(63) = '1' then
311 -- rts == radix tree size, # address bits being translated
312 rts := unsigned('0' & data(62 downto 61) & data(7 downto 5));
313 -- mbits == # address bits to index top level of tree
314 mbits := unsigned('0' & data(4 downto 0));
315 -- set v.shift to rts so that we can use finalmask for the segment check
317 v.mask_size := mbits(4 downto 0);
318 v.pgbase := data(55 downto 8) & x"00";
320 v.state := RADIX_ERROR;
323 v.state := SEGMENT_CHECK;
326 v.state := RADIX_ERROR;
331 when SEGMENT_CHECK =>
332 mbits := '0' & r.mask_size;
333 v.shift := r.shift + (31 - 12) - mbits;
334 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
335 if r.addr(63) /= r.addr(62) or nonzero = '1' then
336 v.state := RADIX_ERROR;
338 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
339 v.state := RADIX_ERROR;
342 v.state := RADIX_LOOKUP;
347 v.state := RADIX_READ_WAIT;
349 when RADIX_READ_WAIT =>
350 if d_in.done = '1' then
351 if d_in.err = '0' then
354 if data(63) = '1' then
356 if data(62) = '1' then
357 -- check permissions and RC bits
359 if r.priv = '1' or data(3) = '0' then
360 if r.iside = '0' then
361 perm_ok := data(1) or (data(2) and not r.store);
363 -- no IAMR, so no KUEP support for now
364 -- deny execute permission if cache inhibited
365 perm_ok := data(0) and not data(5);
368 rc_ok := data(8) and (data(7) or not r.store);
369 if perm_ok = '1' and rc_ok = '1' then
370 v.state := RADIX_LOAD_TLB;
372 v.state := RADIX_ERROR;
373 v.perm_err := not perm_ok;
374 -- permission error takes precedence over RC error
375 v.rc_error := perm_ok;
378 mbits := unsigned('0' & data(4 downto 0));
379 if mbits < 5 or mbits > 16 or mbits > r.shift then
380 v.state := RADIX_ERROR;
383 v.shift := v.shift - mbits;
384 v.mask_size := mbits(4 downto 0);
385 v.pgbase := data(55 downto 8) & x"00";
386 v.state := RADIX_LOOKUP;
390 -- non-present PTE, generate a DSI
391 v.state := RADIX_ERROR;
395 v.state := RADIX_ERROR;
400 when RADIX_LOAD_TLB =>
402 if r.iside = '0' then
417 if r.addr(63) = '1' then
418 effpid := x"00000000";
422 prtable_addr := x"00" & r.prtbl(55 downto 36) &
423 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
424 (effpid(31 downto 8) and finalmask(23 downto 0))) &
425 effpid(7 downto 0) & "0000";
427 pgtable_addr := x"00" & r.pgbase(55 downto 19) &
428 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
431 ((r.pde(55 downto 12) and not finalmask) or (r.addr(55 downto 12) and finalmask))
432 & r.pde(11 downto 0);
438 if tlbie_req = '1' then
441 elsif tlb_load = '1' then
442 addr := r.addr(63 downto 12) & x"000";
444 elsif prtbl_rd = '1' then
445 addr := prtable_addr;
446 tlb_data := (others => '0');
448 addr := pgtable_addr;
449 tlb_data := (others => '0');
453 l_out.invalid <= r.invalid;
454 l_out.badtree <= r.badtree;
455 l_out.segerr <= r.segerror;
456 l_out.perm_error <= r.perm_err;
457 l_out.rc_error <= r.rc_error;
459 d_out.valid <= dcreq;
460 d_out.tlbie <= tlbie_req;
461 d_out.doall <= inval_all;
462 d_out.tlbld <= tlb_load;
464 d_out.pte <= tlb_data;
466 i_out.tlbld <= itlb_load;
467 i_out.tlbie <= tlbie_req;
468 i_out.doall <= inval_all;
470 i_out.pte <= tlb_data;