2 * iceprog -- simple programming tool for FTDI-based Lattice iCE programmers
4 * Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2018 Piotr Esden-Tempski <piotr@esden.net>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 * http://www.ftdichip.com/Support/Documents/AppNotes/AN_108_Command_Processor_for_MPSSE_and_MCU_Host_Bus_Emulation_Modes.pdf
35 // ---------------------------------------------------------
36 // MPSSE / FTDI definitions
37 // ---------------------------------------------------------
39 /* FTDI bank pinout typically used for iCE dev boards
40 * BUS IO | Signal | Control
41 * -------+--------+--------------
42 * xDBUS0 | SCK | MPSSE
43 * xDBUS1 | MOSI | MPSSE
44 * xDBUS2 | MISO | MPSSE
48 * xDBUS6 | CDONE | GPIO
49 * xDBUS7 | CRESET | GPIO
52 struct ftdi_context mpsse_ftdic
;
53 bool mpsse_ftdic_open
= false;
54 bool mpsse_ftdic_latency_set
= false;
55 unsigned char mpsse_ftdi_latency
;
57 /* Not sure if all of these are applicable to the JTAG interface */
60 ISC_NOOP
= 0xFF, /* 0 bits - Non-operation */
61 READ_ID
= 0xE0, /* 24 bits - Read out the 32-bit IDCODE of the device */
62 USERCODE
= 0xC0, /* 24 bits - Read 32-bit usercode */
63 LSC_READ_STATUS
= 0x3C, /* 24 bits - Read out internal status */
64 LSC_CHECK_BUSY
= 0xF0, /* 24 bits - Read 1 bit busy flag to check the command execution status */
65 LSC_REFRESH
= 0x79, /* 24 bits - Equivalent to toggle PROGRAMN pin */
66 ISC_ENABLE
= 0xC6, /* 24 bits - Enable the Offline configuration mode */
67 ISC_ENABLE_X
= 0x74, /* 24 bits - Enable the Transparent configuration mode */
68 ISC_DISABLE
= 0x26, /* 24 bits - Disable the configuration operation */
69 ISC_PROGRAM_USERCODE
= 0xC2, /* 24 bits - Write the 32-bit new USERCODE data to USERCODE register */
70 ISC_ERASE
= 0x0E, /* 24 bits - Bulk erase the memory array base on the access mode and array selection */
71 ISC_PROGRAM_DONE
= 0x5E, /* 24 bits - Program the DONE bit if the device is in Configuration state. */
72 ISC_PROGRAM_SECURITY
= 0xCE, /* 24 bits - Program the Security bit if the device is in Configuration state */
73 LSC_INIT_ADDRESS
= 0x46, /* 24 bits - Initialize the Address Shift Register */
74 LSC_WRITE_ADDRESS
= 0xB4, /* 24 bits - Write the 16 bit Address Register to move the address quickly */
75 LSC_BITSTREAM_BURST
= 0x7A, /* 24 bits - Program the device the whole bitstream sent in as the command operand */
76 LSC_PROG_INCR_RTI
= 0x82, /* 24 bits - Write configuration data to the configuration memory frame at current address and post increment the address, Byte 2~0 of the opcode indicate number of the frames included in the operand field */
77 LSC_PROG_INCR_ENC
= 0xB6, /* 24 bits - Encrypt the configuration data then write */
78 LSC_PROG_INCR_CMP
= 0xB8, /* 24 bits - Decompress the configuration data, then write */
79 LSC_PROG_INCR_CNE
= 0xBA, /* 24 bits - Decompress and Encrypt the configuration data, then write */
80 LSC_VERIFY_INCR_RTI
= 0x6A, /* 24 bits - Read back the configuration memory frame selected by the address register and post increment the address */
81 LSC_PROG_CTRL0
= 0x22, /* 24 bits - Modify the Control Register 0 */
82 LSC_READ_CTRL0
= 0x20, /* 24 bits - Read the Control Register 0 */
83 LSC_RESET_CRC
= 0x3B, /* 24 bits - Reset 16-bit frame CRC register to 0x0000 */
84 LSC_READ_CRC
= 0x60, /* 24 bits - Read 16-bit frame CRC register content */
85 LSC_PROG_SED_CRC
= 0xA2, /* 24 bits - Program the calculated 32-bit CRC based on configuration bit values only into overall CRC register */
86 LSC_READ_SED_CRC
= 0xA4, /* 24 bits - Read the 32-bit SED CRC */
87 LSC_PROG_PASSWORD
= 0xF1, /* 24 bits - Program 64-bit password into the non-volatile memory (Efuse) */
88 LSC_READ_PASSWORD
= 0xF2, /* 24 bits - Read out the 64-bit password before activated for verification */
89 LSC_SHIFT_PASSWORD
= 0xBC, /* 24 bits - Shift in the password to unlock for re-configuration (necessary when password protection feature is active). */
90 LSC_PROG_CIPHER_KEY
= 0xF3, /* 24 bits - Program the 128-bit cipher key into Efuse */
91 LSC_READ_CIPHER_KEY
= 0xF4, /* 24 bits - Read out the 128-bit cipher key before activated for verification */
92 LSC_PROG_FEATURE
= 0xE4, /* 24 bits - Program User Feature, such as Customer ID, I2C Slave Address, Unique ID Header */
93 LSC_READ_FEATURE
= 0xE7, /* 24 bits - Read User Feature, such as Customer ID, I2C Slave Address, Unique ID Header */
94 LSC_PROG_FEABITS
= 0xF8, /* 24 bits - Program User Feature Bits, such as CFG port and pin persistence, PWD_EN, PWD_ALL, DEC_ONLY, Feature Row Lock etc. */
95 LSC_READ_FEABITS
= 0xFB, /* 24 bits - Read User Feature Bits, such as CFH port and pin persistence, PWD_EN, PWD_ALL, DEC_ONLY, Feature Row Lock etc. */
96 LSC_PROG_OTP
= 0xF9, /* 24 bits - Program OTP bits, to set Memory Sectors One Time Programmable */
97 LSC_READ_OTP
= 0xFA, /* 24 bits - Read OTP bits setting */
101 // ---------------------------------------------------------
102 // MPSSE / FTDI function implementations
103 // ---------------------------------------------------------
105 void mpsse_check_rx()
109 int rc
= ftdi_read_data(&mpsse_ftdic
, &data
, 1);
112 fprintf(stderr
, "unexpected rx byte: %02X\n", data
);
116 void mpsse_error(int status
)
119 fprintf(stderr
, "ABORT.\n");
120 if (mpsse_ftdic_open
) {
121 if (mpsse_ftdic_latency_set
)
122 ftdi_set_latency_timer(&mpsse_ftdic
, mpsse_ftdi_latency
);
123 ftdi_usb_close(&mpsse_ftdic
);
125 ftdi_deinit(&mpsse_ftdic
);
129 uint8_t mpsse_recv_byte()
133 int rc
= ftdi_read_data(&mpsse_ftdic
, &data
, 1);
135 fprintf(stderr
, "Read error.\n");
145 void mpsse_send_byte(uint8_t data
)
147 int rc
= ftdi_write_data(&mpsse_ftdic
, &data
, 1);
149 fprintf(stderr
, "Write error (single byte, rc=%d, expected %d).\n", rc
, 1);
154 void mpsse_send_spi(uint8_t *data
, int n
)
159 /* Output only, update data on negative clock edge. */
160 mpsse_send_byte(MC_DATA_OUT
| MC_DATA_OCN
);
161 mpsse_send_byte(n
- 1);
162 mpsse_send_byte((n
- 1) >> 8);
164 int rc
= ftdi_write_data(&mpsse_ftdic
, data
, n
);
166 fprintf(stderr
, "Write error (chunk, rc=%d, expected %d).\n", rc
, n
);
171 void mpsse_xfer_spi(uint8_t *data
, int n
)
176 /* Input and output, update data on negative edge read on positive. */
177 mpsse_send_byte(MC_DATA_IN
| MC_DATA_OUT
| MC_DATA_OCN
);
178 mpsse_send_byte(n
- 1);
179 mpsse_send_byte((n
- 1) >> 8);
181 int rc
= ftdi_write_data(&mpsse_ftdic
, data
, n
);
183 fprintf(stderr
, "Write error (chunk, rc=%d, expected %d).\n", rc
, n
);
187 for (int i
= 0; i
< n
; i
++)
188 data
[i
] = mpsse_recv_byte();
191 uint8_t mpsse_xfer_spi_bits(uint8_t data
, int n
)
196 /* Input and output, update data on negative edge read on positive, bits. */
197 mpsse_send_byte(MC_DATA_IN
| MC_DATA_OUT
| MC_DATA_OCN
| MC_DATA_BITS
);
198 mpsse_send_byte(n
- 1);
199 mpsse_send_byte(data
);
201 return mpsse_recv_byte();
204 void mpsse_set_gpio(uint8_t gpio
, uint8_t direction
)
206 mpsse_send_byte(MC_SETB_LOW
);
207 mpsse_send_byte(gpio
); /* Value */
208 mpsse_send_byte(direction
); /* Direction */
211 int mpsse_readb_low(void)
214 mpsse_send_byte(MC_READB_LOW
);
215 data
= mpsse_recv_byte();
219 int mpsse_readb_high(void)
222 mpsse_send_byte(MC_READB_HIGH
);
223 data
= mpsse_recv_byte();
227 void mpsse_send_dummy_bytes(uint8_t n
)
229 // add 8 x count dummy bits (aka n bytes)
230 mpsse_send_byte(MC_CLK_N8
);
231 mpsse_send_byte(n
- 1);
232 mpsse_send_byte(0x00);
236 void mpsse_send_dummy_bit(void)
239 mpsse_send_byte(MC_CLK_N
);
240 mpsse_send_byte(0x00);
243 void mpsse_jtag_init(){
244 mpsse_send_byte(MC_SETB_LOW
);
245 mpsse_send_byte(0x08); /* Value */
246 mpsse_send_byte(0x0B); /* Direction */
248 /* Reset JTAG State machine */
252 void mpsse_jtag_tms(uint8_t bits
, uint8_t pattern
){
253 mpsse_send_byte(MC_DATA_TMS
| MC_DATA_LSB
| MC_DATA_BITS
);
254 mpsse_send_byte(bits
-1);
255 mpsse_send_byte(pattern
);
258 void mpsse_init(int ifnum
, const char *devstr
, bool slow_clock
)
260 enum ftdi_interface ftdi_ifnum
= INTERFACE_A
;
264 ftdi_ifnum
= INTERFACE_A
;
267 ftdi_ifnum
= INTERFACE_B
;
270 ftdi_ifnum
= INTERFACE_C
;
273 ftdi_ifnum
= INTERFACE_D
;
276 ftdi_ifnum
= INTERFACE_A
;
280 ftdi_init(&mpsse_ftdic
);
281 ftdi_set_interface(&mpsse_ftdic
, ftdi_ifnum
);
283 if (devstr
!= NULL
) {
284 if (ftdi_usb_open_string(&mpsse_ftdic
, devstr
)) {
285 fprintf(stderr
, "Can't find iCE FTDI USB device (device string %s).\n", devstr
);
289 if (ftdi_usb_open(&mpsse_ftdic
, 0x0403, 0x6010) && ftdi_usb_open(&mpsse_ftdic
, 0x0403, 0x6014)) {
290 fprintf(stderr
, "Can't find iCE FTDI USB device (vendor_id 0x0403, device_id 0x6010 or 0x6014).\n");
295 mpsse_ftdic_open
= true;
297 if (ftdi_usb_reset(&mpsse_ftdic
)) {
298 fprintf(stderr
, "Failed to reset iCE FTDI USB device.\n");
302 if (ftdi_usb_purge_buffers(&mpsse_ftdic
)) {
303 fprintf(stderr
, "Failed to purge buffers on iCE FTDI USB device.\n");
307 if (ftdi_get_latency_timer(&mpsse_ftdic
, &mpsse_ftdi_latency
) < 0) {
308 fprintf(stderr
, "Failed to get latency timer (%s).\n", ftdi_get_error_string(&mpsse_ftdic
));
312 /* 1 is the fastest polling, it means 1 kHz polling */
313 if (ftdi_set_latency_timer(&mpsse_ftdic
, 1) < 0) {
314 fprintf(stderr
, "Failed to set latency timer (%s).\n", ftdi_get_error_string(&mpsse_ftdic
));
318 mpsse_ftdic_latency_set
= true;
320 /* Enter MPSSE (Multi-Protocol Synchronous Serial Engine) mode. Set all pins to output. */
321 if (ftdi_set_bitmode(&mpsse_ftdic
, 0xff, BITMODE_MPSSE
) < 0) {
322 fprintf(stderr
, "Failed to set BITMODE_MPSSE on iCE FTDI USB device.\n");
326 // enable clock divide by 5
327 mpsse_send_byte(MC_TCK_D5
);
331 mpsse_send_byte(MC_SET_CLK_DIV
);
332 mpsse_send_byte(119);
333 mpsse_send_byte(0x00);
336 mpsse_send_byte(MC_SET_CLK_DIV
);
337 mpsse_send_byte(0x00);
338 mpsse_send_byte(0x00);
342 void mpsse_close(void)
344 ftdi_set_latency_timer(&mpsse_ftdic
, mpsse_ftdi_latency
);
345 ftdi_disable_bitbang(&mpsse_ftdic
);
346 ftdi_usb_close(&mpsse_ftdic
);
347 ftdi_deinit(&mpsse_ftdic
);