2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.decode_types.all;
8 use work.ppc_fx_insns.all;
9 use work.crhelpers.all;
13 PIPELINE_DEPTH : natural := 2
18 m_in : in Decode2ToMultiplyType;
19 m_out : out MultiplyToWritebackType
23 architecture behaviour of multiply is
24 signal m: Decode2ToMultiplyType;
26 type multiply_pipeline_stage is record
28 insn_type : insn_type_t;
29 data : signed(129 downto 0);
30 write_reg : std_ulogic_vector(4 downto 0);
33 constant MultiplyPipelineStageInit : multiply_pipeline_stage := (valid => '0', insn_type => OP_ILLEGAL, rc => '0', data => (others => '0'), others => (others => '0'));
35 type multiply_pipeline_type is array(0 to PIPELINE_DEPTH-1) of multiply_pipeline_stage;
36 constant MultiplyPipelineInit : multiply_pipeline_type := (others => MultiplyPipelineStageInit);
38 type reg_type is record
39 multiply_pipeline : multiply_pipeline_type;
42 signal r, rin : reg_type := (multiply_pipeline => MultiplyPipelineInit);
44 multiply_0: process(clk)
46 if rising_edge(clk) then
52 multiply_1: process(all)
53 variable v : reg_type;
54 variable d : std_ulogic_vector(129 downto 0);
55 variable d2 : std_ulogic_vector(63 downto 0);
59 m_out <= MultiplyToWritebackInit;
61 v.multiply_pipeline(0).valid := m.valid;
62 v.multiply_pipeline(0).insn_type := m.insn_type;
63 v.multiply_pipeline(0).data := signed(m.data1) * signed(m.data2);
64 v.multiply_pipeline(0).write_reg := m.write_reg;
65 v.multiply_pipeline(0).rc := m.rc;
67 loop_0: for i in 1 to PIPELINE_DEPTH-1 loop
68 v.multiply_pipeline(i) := r.multiply_pipeline(i-1);
71 d := std_ulogic_vector(v.multiply_pipeline(PIPELINE_DEPTH-1).data);
73 case_0: case v.multiply_pipeline(PIPELINE_DEPTH-1).insn_type is
77 d2 := d(63 downto 32) & d(63 downto 32);
79 d2 := d(127 downto 64);
81 --report "Illegal insn type in multiplier";
82 d2 := (others => '0');
85 m_out.write_reg_data <= d2;
86 m_out.write_reg_nr <= v.multiply_pipeline(PIPELINE_DEPTH-1).write_reg;
88 if v.multiply_pipeline(PIPELINE_DEPTH-1).valid = '1' then
90 m_out.write_reg_enable <= '1';
92 if v.multiply_pipeline(PIPELINE_DEPTH-1).rc = '1' then
93 m_out.write_cr_enable <= '1';
94 m_out.write_cr_mask <= num_to_fxm(0);
95 m_out.write_cr_data <= ppc_cmpi('1', d2, x"0000") & x"0000000";
101 end architecture behaviour;