multiply: Move selection of result bits into execute1
[microwatt.git] / multiply.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4
5 library work;
6 use work.common.all;
7
8 entity multiply is
9 generic (
10 PIPELINE_DEPTH : natural := 4
11 );
12 port (
13 clk : in std_logic;
14
15 m_in : in Execute1ToMultiplyType;
16 m_out : out MultiplyToExecute1Type
17 );
18 end entity multiply;
19
20 architecture behaviour of multiply is
21 signal m: Execute1ToMultiplyType := Execute1ToMultiplyInit;
22
23 type multiply_pipeline_stage is record
24 valid : std_ulogic;
25 data : unsigned(127 downto 0);
26 is_32bit : std_ulogic;
27 neg_res : std_ulogic;
28 end record;
29 constant MultiplyPipelineStageInit : multiply_pipeline_stage := (valid => '0',
30 is_32bit => '0', neg_res => '0',
31 data => (others => '0'));
32
33 type multiply_pipeline_type is array(0 to PIPELINE_DEPTH-1) of multiply_pipeline_stage;
34 constant MultiplyPipelineInit : multiply_pipeline_type := (others => MultiplyPipelineStageInit);
35
36 type reg_type is record
37 multiply_pipeline : multiply_pipeline_type;
38 end record;
39
40 signal r, rin : reg_type := (multiply_pipeline => MultiplyPipelineInit);
41 begin
42 multiply_0: process(clk)
43 begin
44 if rising_edge(clk) then
45 m <= m_in;
46 r <= rin;
47 end if;
48 end process;
49
50 multiply_1: process(all)
51 variable v : reg_type;
52 variable d : std_ulogic_vector(127 downto 0);
53 variable d2 : std_ulogic_vector(63 downto 0);
54 variable ov : std_ulogic;
55 begin
56 v.multiply_pipeline(0).valid := m.valid;
57 v.multiply_pipeline(0).data := unsigned(m.data1) * unsigned(m.data2);
58 v.multiply_pipeline(0).is_32bit := m.is_32bit;
59 v.multiply_pipeline(0).neg_res := m.neg_result;
60
61 loop_0: for i in 1 to PIPELINE_DEPTH-1 loop
62 v.multiply_pipeline(i) := r.multiply_pipeline(i-1);
63 end loop;
64
65 if v.multiply_pipeline(PIPELINE_DEPTH-1).neg_res = '0' then
66 d := std_ulogic_vector(v.multiply_pipeline(PIPELINE_DEPTH-1).data);
67 else
68 d := std_ulogic_vector(- signed(v.multiply_pipeline(PIPELINE_DEPTH-1).data));
69 end if;
70
71 ov := '0';
72 if v.multiply_pipeline(PIPELINE_DEPTH-1).is_32bit = '1' then
73 ov := (or d(63 downto 31)) and not (and d(63 downto 31));
74 else
75 ov := (or d(127 downto 63)) and not (and d(127 downto 63));
76 end if;
77
78 m_out.result <= d;
79 m_out.overflow <= ov;
80 m_out.valid <= v.multiply_pipeline(PIPELINE_DEPTH-1).valid;
81
82 rin <= v;
83 end process;
84 end architecture behaviour;