multiply.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.decode_types.all;
   8
   9 entity multiply is
  10     generic (
  11         PIPELINE_DEPTH : natural := 16
  12         );
  13     port (
  14         clk   : in std_logic;
  15
  16         m_in  : in Execute1ToMultiplyType;
  17         m_out : out MultiplyToExecute1Type
  18         );
  19 end entity multiply;
  20
  21 architecture behaviour of multiply is
  22     signal m: Execute1ToMultiplyType;
  23
  24     type multiply_pipeline_stage is record
  25         valid     : std_ulogic;
  26         insn_type  : insn_type_t;
  27         data      : signed(129 downto 0);
  28         is_32bit  : std_ulogic;
  29     end record;
  30     constant MultiplyPipelineStageInit : multiply_pipeline_stage := (valid => '0',
  31                                                                      insn_type => OP_ILLEGAL,
  32                                                                      is_32bit => '0',
  33                                                                      data => (others => '0'));
  34
  35     type multiply_pipeline_type is array(0 to PIPELINE_DEPTH-1) of multiply_pipeline_stage;
  36     constant MultiplyPipelineInit : multiply_pipeline_type := (others => MultiplyPipelineStageInit);
  37
  38     type reg_type is record
  39         multiply_pipeline : multiply_pipeline_type;
  40     end record;
  41
  42     signal r, rin : reg_type := (multiply_pipeline => MultiplyPipelineInit);
  43 begin
  44     multiply_0: process(clk)
  45     begin
  46         if rising_edge(clk) then
  47             m <= m_in;
  48             r <= rin;
  49         end if;
  50     end process;
  51
  52     multiply_1: process(all)
  53         variable v : reg_type;
  54         variable d : std_ulogic_vector(129 downto 0);
  55         variable d2 : std_ulogic_vector(63 downto 0);
  56         variable ov : std_ulogic;
  57     begin
  58         v := r;
  59
  60         m_out <= MultiplyToExecute1Init;
  61
  62         v.multiply_pipeline(0).valid := m.valid;
  63         v.multiply_pipeline(0).insn_type := m.insn_type;
  64         v.multiply_pipeline(0).data := signed(m.data1) * signed(m.data2);
  65         v.multiply_pipeline(0).is_32bit := m.is_32bit;
  66
  67         loop_0: for i in 1 to PIPELINE_DEPTH-1 loop
  68             v.multiply_pipeline(i) := r.multiply_pipeline(i-1);
  69         end loop;
  70
  71         d := std_ulogic_vector(v.multiply_pipeline(PIPELINE_DEPTH-1).data);
  72         ov := '0';
  73
  74         -- TODO: Handle overflows
  75         case_0: case v.multiply_pipeline(PIPELINE_DEPTH-1).insn_type is
  76             when OP_MUL_L64 =>
  77                 d2 := d(63 downto 0);
  78                 if v.multiply_pipeline(PIPELINE_DEPTH-1).is_32bit = '1' then
  79                     ov := (or d(63 downto 31)) and not (and d(63 downto 31));
  80                 else
  81                     ov := (or d(127 downto 63)) and not (and d(127 downto 63));
  82                 end if;
  83             when OP_MUL_H32 =>
  84                 d2 := d(63 downto 32) & d(63 downto 32);
  85             when OP_MUL_H64 =>
  86                 d2 := d(127 downto 64);
  87             when others =>
  88                 --report "Illegal insn type in multiplier";
  89                 d2 := (others => '0');
  90         end case;
  91
  92         m_out.write_reg_data <= d2;
  93         m_out.overflow <= ov;
  94
  95         if v.multiply_pipeline(PIPELINE_DEPTH-1).valid = '1' then
  96             m_out.valid <= '1';
  97         end if;
  98
  99         rin <= v;
 100     end process;
 101 end architecture behaviour;