nlnet_2019_video.mdwn

   1 # NL.net proposal
   2
   3 ## Project name
   4
   5 The Libre-RISCV SoC, Video Decoding
   6
   7 ## Website / wiki
   8
   9 <https://libre-riscv.org/nlnet_2019_video>
  10
  11 Please be short and to the point in your answers; focus primarily on
  12 the what and how, not so much on the why. Add longer descriptions as
  13 attachments (see below). If English isn't your first language, don't
  14 worry - our reviewers don't care about spelling errors, only about
  15 great ideas. We apologise for the inconvenience of having to submit in
  16 English. On the up side, you can be as technical as you need to be (but
  17 you don't have to). Do stay concrete. Use plain text in your reply only,
  18 if you need any HTML to make your point please include this as attachment.
  19
  20 ## Abstract: Can you explain the whole project and its expected outcome(s).
  21
  22 The Libre RISC-V SoC is being developed to provide a privacy-respecting
  23 modern processor, developed transparently and as libre to the bedrock
  24 as possible.
  25
  26 One of the main "hardware accelerated blocks" of any processor intended for user applications is Video Encode and Decode. This usually means an opaque, proprietary piece of hardware, and it usually comes with proprietary firmware as well.
  27
  28
  29 In a
  30
  31 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  32
  33 Luke Leighton is an ethical technology specialist who has a consistent
  34 24-year track record of developing code in a real-time transparent
  35 (fully libre) fashion, and in managing Software Libre teams.  He is the
  36 lead developer on the Libre RISC-V SoC.
  37
  38 Jean-Paul Chaput is the lead engineer on the Alliance and Coriolis2
  39 tools for VLSI backend layout, from the Laboratoire d'Informatique de
  40 Paris 6.
  41
  42 # Requested Amount
  43
  44 EUR 50,000.
  45
  46 # Explain what the requested budget will be used for?
  47
  48 The key initial milestone for the 2018 NLNet Libre RISC-V SoC Project
  49 is the FPGA target: a working design that can run in an FPGA at approximately
  50 50Mhz.  The next logical step is to do the layout.
  51
  52 However, FPGA targets have some quirks which help accelerate FPGAs (not ASICs):
  53 an on-board DSP, specialist memory, and so on.  Without these "crutches"
  54 the design must be augmented and adapted to suit ASIC layout.
  55
  56 As we are using nmigen for the HDL front-end and yosys for the HDL
  57 back-end, we will need to work with the nmigen developers in order to
  58 augment nmigen to cope with the task of creating "netlists" suitable for
  59 ASICs.  Whilst yosys (the actual "netlist" generator) has been utilised
  60 for this task repeatedly and successfully, and whilst the prior version,
  61 "migen", was also used, nmigen has not yet been ASIC proven.
  62
  63 Once a "netlist" is available, the Coriolis2 VLSI tool will be used to
  64 actually create the layers of the chip.  Given the size and capabilities
  65 of the chip, we anticipate issues here, which we will need the support
  66 of LIP6's engineers to solve.
  67
  68 The layout itself is also dependent on what is called "Cell Libraries".
  69 One is "NSXLIB" which contains OR and AND gates to create MUXes and XORs.
  70 Another is an "SRAM" Library (memory), and another is a "GPIO" Cell
  71 Library.  Chips4Makers will be working on these low-level blocks for
  72 us (under a separate Programme), however we again anticipate issues -
  73 related to Foundry NDAs - which will hamper the communications process.
  74
  75 So therefore, the requested budget will be used for:
  76
  77 * Augmentation and adaptation of the Libre RISC-V SoC HDL to ASIC layout
  78 * Engineers to work on the layout using Alliance / Coriolos2 VLSI, from lip6
  79 * Engineers to bug-fix or augment Alliance / Coriolis2
  80 * Essential augmentations to nmigen to make it ASIC-layout-capable
  81
  82 All of these will be and are entirely libre-licensed software: there will
  83 be no proprietary software tools utilised in this process.  Note that
  84
  85
  86 # Does the project have other funding sources, both past and present?
  87
  88 The overall project has sponsorship from Purism as well as a prior grant
  89 from NLNet.  However that is for specifically covering the development
  90 of the RTL (the hardware source code).
  91
  92 There is no source of funds for the work on the *next* stage: the actual
  93 VLSI ASIC Layout.  Chips4Makers is however putting in an *additional*
  94 (and separate) funding application for the stage after *this*: the
  95 creation of the Cell Libraries that will be used in the VLSI ASIC Layout.
  96
  97 All these three projects are separate and distinct (despite being related
  98 to the same CPU), and funding may not cross over from one project to
  99 the other.
 100
 101 # Compare your own project with existing or historical efforts.
 102
 103 There are several Open VLSI Tool suites:
 104
 105 * GNU Electric: https://www.gnu.org/software/electric/
 106 * MAGIC: http://opencircuitdesign.com/magic/
 107 * The OpenROAD Project: https://theopenroadproject.org/ (using MAGIC)
 108 * QFlow: http://opencircuitdesign.com/qflow/
 109 * Toped: http://www.toped.org.uk/
 110
 111 and a few more.  We choose Coriolis2 because of its python interface.
 112 The VLSI Layout is actually done as a *python* program.  With nmigen
 113 (the HDL) being in python, we anticipate the same OO benefits to be
 114 achievable in coriolis2 as well.
 115
 116 The case for the Libre RISC-V SoC itself was made already in the initial
 117 2018.02 proposal.  That has not changed: there are no Libre / Open Projects
 118 approaching anything like the complexity and product market opportunities
 119 of the Libre RISC-V SoC, which is being designed to be a quad-core 800mhz
 120 multi-issue out-of-order design.  All other Libre / Open processors such
 121 as Raven, and many more, have a goal set in advance not to exceed around
 122 the 350mhz mark, and are single-core.
 123
 124 Other projects which are "open", such as the Ariane Processor, are
 125 developed by universities, and in the case of Ariane were *SPECIFICALLY*
 126 designed by and for the use of proprietary toolchains, such as those from
 127 Cadence, Synopsys and Mentor Graphics.  Despite the source code being
 128 "open", there was absolutely no expectation that the processor of the
 129 same capability as the Libre RISC-V SoC would use Libre / Open tools.
 130
 131 Although our first ASIC (thanks to Chips4Makers) will be only 180nm,
 132 single-core and a maximum of around 350mhz, this is just the first
 133 stepping stone to a much larger processor.
 134
 135 ## What are significant technical challenges you expect to solve during the project, if any?
 136
 137 Some of these have been mentioned above:
 138
 139 * NDAs by Foundries may interfere with the ability for Chips4Makers to
 140   communicate with LIP6 regarding the necessary changes to NSXLIB which
 141   meet the TSMC Foundry "Design Rule Checks" (DRCs).
 142 * Bugs or missing features in nmigen, yosys, coriolis2, NSXLIB, OpenRAM,
 143   and the knock-on implications throughout the chain, right the way up
 144   to the *actual* Libre RISC-V SoC's HDL source code itself, all need to
 145   be dealt with.
 146 * Circuit simulation and unit testing is going to be a major factor, and
 147   a huge utilisation of Computing power.  Machines with "only" 16 GB of RAM
 148   and high-end quad-core processors are going to be hopelessly inadequate.
 149
 150 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 151
 152 LIP6 have their own mailing list for the (transparent) discussion of
 153 issues related to coriolis2: <alliance-users@asim.lip6.fr>.  The Libre RISC-V
 154 SoC has a full set of resources for Libre Project Management and development:
 155 mailing list, bugtracker, git repository and wiki - all listed here:
 156 <https://libre-riscv.org/>
 157
 158 In addition, we have a Crowdsupply page
 159 <https://www.crowdsupply.com/libre-risc-v/m-class> which provides a public
 160 gateway, and heise.de, reddit, phoronix, slashdot and other locations have
 161 all picked up the story.  The list is updated and maintained here:
 162 <https://libre-riscv.org/3d_gpu/>
 163
 164 # Extra info to be submitted
 165
 166 * <http://libre-riscv.org/3d_gpu/>
 167 * <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
 168 * <https://nlnet.nl/project/Libre-RISCV/>
 169 * <https://chips4makers.io/blog/>
 170