nlnet_2019_wishbone_streaming.mdwn

   1 # NL.net proposal
   2
   3 * NLNet Project Page <https://nlnet.nl/project/WishboneStreaming/>
   4 * 2019-10-043
   5 * Top Level bugreport <http://bugs.libre-riscv.org/show_bug.cgi?id=175>
   6
   7 ## Project name
   8
   9 The Libre RISC-V SoC, Wishbone Streaming Proposal
  10
  11 ## Website / wiki
  12
  13 <https://libre-riscv.org/nlnet_2019_wishbone_streaming>
  14
  15 Please be short and to the point in your answers; focus primarily on
  16 the what and how, not so much on the why. Add longer descriptions as
  17 attachments (see below). If English isn't your first language, don't
  18 worry - our reviewers don't care about spelling errors, only about
  19 great ideas. We apologise for the inconvenience of having to submit in
  20 English. On the up side, you can be as technical as you need to be (but
  21 you don't have to). Do stay concrete. Use plain text in your reply only,
  22 if you need any HTML to make your point please include this as attachment.
  23
  24 ## Abstract: Can you explain the whole project and its expected outcome(s).
  25
  26 In projects such as the Libre RISC-V SoC, commercial grade System-on-Chip
  27 (SoC) bus infrastructure is needed. Nowadays this often means AMBA AXI4,
  28 AXI4-lite or AXI4-Stream, all published by ARM Limited. The AXI family is
  29 "royality-free" and it is not only patented but its patent holder has
  30 begun denying licenses due to the US Trade War.
  31
  32 The main alternative with large adoption is Wishbone, which is an Open
  33 Standard in contrast to AXI. However Wishbone does not have a "streaming"
  34 capability, which is typically needed for high-throughput data pathes and
  35 interfaces, e.g. for video applications and High-Performance Computing
  36 (HPC).
  37
  38 Therefore this project will write up an enhancement to the Wishbone B4 SoC
  39 Bus, provide Reference Implementations and Bus Function Models (BFM) which
  40 easily allows unit tests for all Wishbone BFM users. For demonstration
  41 we like to implement an example peripheral (here, an audio interface, for
  42 the Libre RISC-V SoC) also. This demonstrations proves our concept also.
  43
  44 A secondary objective will be to seek out Reference Implementations for
  45 Wishbone Master and Slave, provide formal correctness proofs, and add
  46 additional example peripherals - non-streaming ones - as resources permit.
  47
  48 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  49
  50 Luke Leighton is an ethical technology specialist who has a consistent
  51 24-year track record of developing code in a real-time transparent
  52 (fully libre) fashion, and in managing Software Libre teams. He is the
  53 lead developer on the Libre RISC-V SoC.
  54
  55 Hagen Sankowski is a Senior ASIC Design Engineer, with 20-year Experiences
  56 thru the whole Design Flow, from Digital Entry (Verilog HDL, VHDL) to
  57 DSM Backend and back. He has FPGA knowledge for Xilinx, Altera, Lattice
  58 and MicroSemi. Inventor and Patentee for a FPGA structure. Open Source
  59 Evangelist, member of the LibreSilicon project Team also.
  60
  61 # Requested Amount
  62
  63 EUR 50,000.
  64
  65 # Explain what the requested budget will be used for?
  66
  67 Improve the Wishbone B4 Specification to add streaming capability,
  68 comparable to AXI4-Stream, and feed the improvements back into the
  69 current stewardship for next Wishbone release.
  70
  71 Design Reference Implementations in nmigen and (System-)Verilog, Bus
  72 Function Models and other functionality in SystemVerilog for verification
  73 with full unit tests aiming best code coverage.
  74
  75 Use some of the Libre RISC-V SoC peripherals as a test platform
  76 and demonstrator (I2S Audio Streaming) for the proposed standard
  77 modifications.
  78
  79 Traveling expenses for presenting the Wishbone improvements to the RISC-V
  80 community once at the annual ORConf in 2020.
  81
  82 As a secondary objective: seek out existing (non-streaming) Wishbone
  83 Master and Slave Bus implementations (or implement them if necessary),
  84 provide formal proof unit tests of their correctness, and add additional
  85 example peripherals.
  86
  87 # Does the project have other funding sources, both past and present?
  88
  89 The concept of extending Wishbone to have streaming capability is entirely
  90 new: it has no source of funding.
  91
  92 The Libre RISC-V SoC has funding from NLNet under a 2018 Grant: it was
  93 intending to use AXI4 prior to the U.S. Trade War.
  94
  95 # Compare your own project with existing or historical efforts.
  96
  97 AXI4 has streaming (as AXI4-Stream) but it is proprietary and patented.
  98
  99 TileLink is an alternative protocol (with roots in the RISC-V academic
 100 community) but it is relatively new, quite complex, and does not have
 101 the same adoption as Wishbone.
 102
 103 There do exist a number of pre-existing Wishbone Bus Master and
 104 Slave implementations: Wishbone has been around for a significantly
 105 long time and has been the de-facto choice in the Libre/Open Hardware
 106 community. Formal correctness proofs for Wishbone have been written by
 107 Dan Gisselquist in SystemVerilog, but none are written in nmigen.
 108
 109 ## What are significant technical challenges you expect to solve during the project, if any?
 110
 111 This is a straightforward project. However the timing issues involved
 112 with Bus Negotiation can be awkward to get right and may need formal
 113 proofs to properly verify.  Dan Gisselquist's work in his area shows
 114 how it can be done.
 115
 116 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes
 117
 118 As mentioned in the 2018 submission, the Libre RISC-V
 119 SoC has a full set of resources for Libre Project Management and development:
 120 mailing list, bugtracker, git repository and wiki - all listed here:
 121 <https://libre-riscv.org/>
 122
 123 In addition, we have a Crowdsupply page
 124 <https://www.crowdsupply.com/libre-risc-v/m-class> which provides a public
 125 gateway, and heise.de, reddit, phoronix, slashdot and other locations have
 126 all picked up the story.  The list is updated and maintained here:
 127 <https://libre-riscv.org/3d_gpu/>
 128
 129 # Extra info to be submitted
 130
 131 * <http://libre-riscv.org/3d_gpu/>
 132 * <https://nlnet.nl/project/Libre-RISCV/>
 133 * <https://cdn.opencores.org/downloads/wbspec_b4.pdf>
 134 * <https://zipcpu.com/zipcpu/2017/11/07/wb-formal.html>