nlnet_2022_ongoing/discussion.mdwn

   1 # questions 05 oct 2022
   2
   3 context is from other [[nlnet_2022_opf_isa_wg/discussion]] on 2022-08-051
   4
   5 **
   6     Again there should be a breakdown of the main tasks, and the associated effort.
   7     And a clarification what rates you used.
   8     (I'm assuming these are the same, but I've learned not to assume...)
   9 **
  10
  11 yes EUR 3,000 / mo as a yardstick works out ok in practice.
  12
  13 tasks, adapted (OpenCAPI is now a secret closed Standard, assigned to a
  14 group backed by Intel!)
  15
  16 * 2-3 months: Dynamic Partitioned SIMD for nmigen
  17 * 3-4 months: Completion of IEEE754 FP Formal Correctness Proofs
  18 * 3-5 months: Completion of an In-Order Single-Issue core implementing SVP64
  19 * 3-4 months: Addition of the IEEE754 FPU to the Core
  20 * 3-4 months: Addition of other ALUs and pipelines
  21 * 4-5 months: Addition of SMP (multi-core) support (lots of research here,
  22   need help from IBM / Microwatt, the SMP Memory Model is conprehensive)
  23 * 3-4 months: Running under Verilator and on FPGAs (big ones)
  24 * 4-5 months: Continued documentation, attendance of Conferences online
  25 * 4-5 months: Begin investigating Multi-Issue Out-of-Order
  26 * 2-3 months plus hosting costs: Establishment and management of CI
  27 * 2? months?: two Bitmain 250 FPGA porting (thanks to UOregon)
  28
  29 lower estimate is around 33 months, upper limit is 44, so a EUR 100,000
  30 budget @ EUR 3,000/mo is within target (just). may need adjusting or some
  31 tasks removing, to fit. we cannot risk committing to tasks at too low a
  32 rate to be able to attract interest and committment.
  33
  34 Again however I do not have a problem with reducing the scope of this one
  35 to only EUR 50,000 to cover some of the less ambitious tasks, and the
  36 necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) first.
  37
  38 **
  39     What would be the concrete (high level) outcome of that project -
  40     where would the grant get us? Would there be a new test chip made
  41     during the lifespan of the project?
  42 **
  43
  44 Answering on the ASIC first: it is a little early to tell.  Coriolis2 needs Timing
  45 based Routing completed in order to tackle lower geometries (even 90nm),
  46 https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049 - and sky130
  47 is far too small an allocation (12 mm^2 when we need around 100).
  48 Given the amount of time it took (I have to admit it was a major time-sink for me)
  49 I am happy to wait until coriolis2 is more feature-ready.  Powerful FPGAs
  50 get us a long way.
  51
  52 The concrete outcomes:
  53
  54 * A greatly increased strategic capacity of nmigen HDL: full Object-Orientated
  55   Abstraction of its core Language Features.  Opportunities then open up
  56   to perform strict type checking, length checking, other types of Arithmetic
  57   (Complex numbers, Galois Field) and other "filters" as
  58   3rd party extensions, of which the Dynamic SIMD Partitioning created under
  59   2019-02-012 would be the first big showcase.
  60 * A modern well-documented IEEE754 Floating-Point Library, with Formal Correctess
  61   Proofs using modern FOSSHW tools is a big deal in its own right. The only
  62   other Libre Formal Proof is for an older version of IEEE754, we will
  63   target 2008 and 2019 semantics.
  64