1 # questions 17 aug 2023
3 * <https://bugs.libre-soc.org/show_bug.cgi?id=961#c5>
5 ## Discussion from meeting on the 23rd August 2023 21:00 UTC+1
9 * There is no overlap, as #976 tackled a different issue (and was already complete
11 * "observe in the child tasks that the entire budget *has* already been allocated to subtasks.... *none of which* overlap (or are a duplicate of) #972"
12 * Bug #1003 does however build on the work from #972.
13 * Added to comment 0 of bug #1003 to clarify that it builds on top of #972.
15 **TODO: just put clear message describing task. No "Edit: this etc etc"**
19 * Build means that Sadoon provides documentation for setting up a SFFS port
21 * Stage 3 tar archive file for Gentoo is now available,
22 see [instructions](https://libre-soc.org/SFFS/gentoo_bootstrap/).
23 * Debian scripts are still being worked on as of 23rd Aug.
24 * All files required are hosted either on Libre-SOC's ftp or git.
25 * Patching qemu has been discovered to be out-of-scope for this task
26 (far too much work). Sadoon will be creating (or adding sesction to
27 Gentoo/Debian pages) a wiki page describing the
28 work he went through with qemu.
30 **TODO: sadoon, edit the "TODOs" and "DONEs" to include the relevant bugreports.**
32 **TODO: sadoon, complete the descriptions in comment zeros of each subtask of #999.**
36 * Jacob is still working on figuring out the subtasks which should be focused
37 on for the scope of the On-Going grant.
39 **NOT NEEDED at this stage, can be submitted later. we need to MOVE and get the MoU signed**
43 * Jacob mentioned there are two major parts
45 1. Decoder/fetch pipeline
48 Cesar likely do the former, Jacob could do the latter.
50 **CORRECTION: JACOB to do both.**
54 * Create the framework for testing (or choose existing)
55 (jacob: important clarification -- afaict this task is adding new `StateRunner`
56 and `State` subclasses for FPGA/verilator/etc.
57 This task is *not* for creating a new framework or choosing an existing framework,
58 we already have one with implementations for pypowersim, nmigen simulation of the
59 libre-soc core, and `ExpectedState`. maybe also QEMU through GDB, icr.)
60 * Add specialisation for pypowersim, microwatt (verilator), FPGA.
61 * Cavatools out of scope.
62 * Builds on top of <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/state.py;hb=c23202498ae30addf04ab4c1e0d7262cc825cd45>?
63 * Initially pypowersim tested against qemu, then FPGA.
64 * For Simple-V/SVP64 only pypowersim implementation right now.
65 SoC HDL has small subset of SVP64.
68 ### Automated method for removing non-MOU things
70 * Jacob added a feature to automatically remove non-MOU strings.
73 # questions 05 oct 2022
75 context is from other [[nlnet_2022_opf_isa_wg/discussion]] on 2022-08-051.
76 mailing list <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-October/005363.html>
79 Again there should be a breakdown of the main tasks, and the associated effort.
80 And a clarification what rates you used.
81 (I'm assuming these are the same, but I've learned not to assume...)
84 yes EUR 3,000 / mo as a yardstick works out ok in practice.
86 tasks, adapted (OpenCAPI is now a secret closed Standard, assigned to a
87 group backed by Intel!)
89 * 2-3 months: Dynamic Partitioned SIMD for nmigen
90 * 5-6 months: Continuation of IEEE754 FP Formal Correctness Proofs, addition
91 of FP Rounding Modes and Power ISA Flags
92 * 3-5 months: Completion of an In-Order Single-Issue core implementing SVP64
93 * 3-4 months: Addition of the IEEE754 FPU to the Core
94 * 3-4 months: Addition of other ALUs and pipelines
95 * 4-5 months: Addition of SMP (multi-core) support (lots of research here,
96 need help from IBM / Microwatt, the SMP Memory Model is conprehensive)
97 * 3-4 months: Running under Verilator and on FPGAs (big ones)
98 * 4-5 months: Continued documentation, attendance of Conferences online
99 * 4-5 months: Begin investigating Multi-Issue Out-of-Order
100 * 2-3 months plus hosting costs: Establishment and management of CI
101 * 2? months?: two Bitmain 250 FPGA porting (thanks to UOregon)
103 lower estimate is around 35 months, upper limit is 46, so a EUR 100,000
104 budget @ EUR 3,000/mo is within target (just). may need adjusting or some
105 tasks removing, to fit. we cannot risk committing to tasks at too low a
106 rate to be able to attract interest and committment.
108 Again however I do not have a problem with reducing the scope of this one
109 to only EUR 50,000 to cover some of the less ambitious tasks, with the
110 necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) being first
111 priority then a second Grant following up to continue.
114 What would be the concrete (high level) outcome of that project -
115 where would the grant get us? Would there be a new test chip made
116 during the lifespan of the project?
119 Answering on the ASIC first: it is a little early to tell. Coriolis2 needs Timing
120 based Routing completed in order to tackle lower geometries (even 90nm),
121 https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049.
123 is far too small an allocation (12 mm^2 when we need around 100), we
124 really need sky90 which as i understand is still being negotiated and set up.
126 Given the amount of time ls180 took (I have to admit it was a major time-sink for me)
127 as a "learning exercise" the 2019-10-029 project was perfect.
128 However as far as "value for money" is concerned, a repeat is honestly
129 less valuable. That said: when it is ready, RED Semiconductor
130 *will* be picking up the Libre-SOC core and taking it to Silicon
131 (28 nm or below). For this Grant Proposal, powerful FPGAs will
134 The concrete outcomes:
136 * A greatly increased strategic capacity of nmigen HDL: full Object-Orientated
137 Abstraction of its core Language Features. Opportunities then open up
138 to perform strict type checking, length checking, other types of Arithmetic
139 (Complex numbers, Galois Field) and other "filters" as
140 3rd party extensions, of which the Dynamic SIMD Partitioning Library created under
141 2019-02-012 would be the first big showcase.
142 * A modern well-documented IEEE754 Floating-Point Library, with Formal Correctess
143 Proofs using modern FOSSHW tools (smt2, symbiyosis) is a big deal in its own right,
144 and something worth aiming for.
146 other Libre Formal Proof is Academically developed
147 for an older version of IEEE754: we will
148 target 2008 and 2019 semantics.
149 * An actual "on-the-ground" realisation of Simple-V in a useable Core, whereas at
150 present it is Simulations only and the cavatools Cycle-accurate Simulator
151 (2021-08-071) is not quite the same thing (userspace binaries only in cavatools,
152 no Virtual Memory, for a start). SMP Support in particular would be strategically
153 very valuable to have, it greatly expands the commercial viability.
154 * A lot larger "eat own dogfood" hosting solution, the NGI POINTER Grant paid for
155 an IBM POWER9 Server which lends us credibility but it needs to be put to
158 In other words, mostly "low-level strategic outcomes" on the way to success :)