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[libreriscv.git] / nlnet_2022_opf_isa_wg.mdwn
1 # NL.net proposal
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3
4 ## Project name
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6 OpenPOWER ISA RFCs
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8 ## Website / wiki
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10 <https://libre-soc.org/nlnet_2022_opf_isa_wg>
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12 Please be short and to the point in your answers; focus primarily on
13 the what and how, not so much on the why. Add longer descriptions as
14 attachments (see below). If English isn't your first language, don't
15 worry - our reviewers don't care about spelling errors, only about
16 great ideas. We apologise for the inconvenience of having to submit in
17 English. On the up side, you can be as technical as you need to be (but
18 you don't have to). Do stay concrete. Use plain text in your reply only,
19 if you need any HTML to make your point please include this as attachment.
20
21 ## Abstract: Can you explain the whole project and its expected outcome(s).
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23
24 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
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26
27 # Requested Amount
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29 EUR 100,000.
30
31 # Explain what the requested budget will be used for?
32
33 * Design and fabrication of Libre/Open Hardware Dual FPGA Carrier
34 boards (most likely accepting OrangeCrab as a module)
35 * Porting of both LibreBMC and OpenBMC to the FPGA Board
36 * Implementation of *server* side LPC (client-side already exists)
37 * Verilator simulation of both client and server side LPC
38 and testing of the two simulations back-to-back
39
40 # Compare your own project with existing or historical efforts.
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42
43 ## What are significant technical challenges you expect to solve during the project, if any?
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45
46
47 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
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49
50 # Extra info to be submitted
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52 * TODO URLs etc