nlnet_2022_opf_isa_wg.mdwn

   1 # NL.net proposal
   2
   3
   4 ## Project name
   5
   6 OpenPOWER ISA RFCs
   7
   8 ## Website / wiki
   9
  10 <https://libre-soc.org/nlnet_2022_opf_isa_wg>
  11
  12 Please be short and to the point in your answers; focus primarily on
  13 the what and how, not so much on the why. Add longer descriptions as
  14 attachments (see below). If English isn't your first language, don't
  15 worry - our reviewers don't care about spelling errors, only about
  16 great ideas. We apologise for the inconvenience of having to submit in
  17 English. On the up side, you can be as technical as you need to be (but
  18 you don't have to). Do stay concrete. Use plain text in your reply only,
  19 if you need any HTML to make your point please include this as attachment.
  20
  21 ## Abstract: Can you explain the whole project and its expected outcome(s).
  22
  23 The current NLnet funding to date has allowed Libre-SOC to develop
  24 one of the most powerful Scalable Vector ISAs in the world.
  25 The 25-year-old Power ISA, developed and curated by IBM, was
  26 transferred to the OpenPOWER Foundation, and is the basis on
  27 which, with NLnet EU funding, we have based
  28 Simple-V, the Draft Scalable Vector Extension.
  29
  30 Simple-V *needs* to be submitted to the OPF ISA Working Group,
  31 for formal discussion and inclusion. Given that it is 380
  32 pages we expect this to be done carefully and incrementally.
  33 https://ftp.libre-soc.org/simple_v_spec.pdf
  34
  35 However the
  36 process of submitting RFCs (Requests For Change), at the time of writing,
  37 still has not been publicly announced and opened up. We expect it
  38 to be very soon, but obviously could not begin any RFC Submission
  39 as part of earlier NLnet funding.  The timing is now right.
  40
  41 We will become publicly informed very shortly of the procedures but anticipate
  42 it to include development and submission of Compliance Test Suites
  43 (already partly covered by Simple-V unit tests, kindly funded by NLnet)
  44 as well as ongoing work on the Simulator.
  45
  46 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  47
  48 A lot! a full list is maintained here <https://libre-soc.org/nlnet_proposals/>
  49 and includes
  50
  51 * the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma, with support for FP Formal Proofs added to symbiyosis;
  52 * the world's first in-place Discrete Cosine Transform algorithm;
  53 * Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs of Sorbonne University)
  54  to do an 800,000 transistor fully automated RTL2GDSII
  55 tape-out;
  56 * development of a 180nm Power ISA 3.0 "Test ASIC", the largest fully FOSSHW
  57   ASIC ever taped-out in Europe (and funded by Horizon 2020)
  58 * development of an Interoperability "Test API" for Power ISA systems,
  59   with thousands of unit tests.
  60
  61 and much more. The side-benefits alone for EU citizens are enormous.
  62
  63 # Requested Amount
  64
  65 EUR 100,000.
  66
  67 # Explain what the requested budget will be used for?
  68
  69 Time and resource, primarily manpower, to prepare and submit the documentation
  70 to OPF. To give us legal compliance for the development
  71 work carried out over the past four years, as part of the
  72 transfer to the OpenPOWER Foundation.
  73
  74 * ongoing communication with the OpenPOWER Foundation ISA Working Group
  75 * preparation of a large number of RFCs (380 pages total so far) through
  76   the External RFC Process
  77 * for each RFC accepted, work needs to be done with IBM to submit Power ISA Spec
  78   changes
  79 * for each RFC accepted, a Compliance Test Suite must be written
  80 * for each Compliance Test Suite written the results must be
  81   confirmed correct by inspection (hence the Simulator) which has
  82   as we already discovered been quite a lot of work
  83 * Along the way we aim to continue developing the "Test API" which
  84   allows running thousands of unit tests on multiple systems and
  85   cross-checking the results.  Currently we have Simulator, some
  86   "Expected Results", and the Libre-SOC HDL as well as qemu.
  87   We aim to add cavatools, gem5, Microwatt and stand-alone binary
  88   auto-generation for running on IBM POWER9 as well as Libre-SOC
  89   and Microwatt FPGAs.
  90
  91 # Compare your own project with existing or historical efforts.
  92
  93 We are developing a Cray-style Scalable Vector ISA Extension for
  94 the Supercomputing-class Power ISA.  Similar historic ISAs include
  95 Cray YMP1, ETA-19, Cyber CDC 205. More recent is the NEC SX Aurora.
  96 They are all proprietary systems: Libre-SOC's efforts are entirely
  97 FOSSHW.
  98
  99 Open Scalable Vector ISAs include MRISC32/64 (in early development) and
 100 RISC-V RVV. Advocates of RISC-V have been discovering to their dismay
 101 that RVV and RISC-V ISA has fundamental design issues that cannot be fixed.
 102 Additionally, submission of RISCV ISA modifications requires RISCV Foundation
 103 Membership which puts us under impossible conflict of interest with
 104 Full Transparency Conditions not only with NLnet but also with
 105 EU Auditing Requirements.  By direct contrast OPF External RFC Submission
 106 does not require Secrecy.
 107
 108 ## What are significant technical challenges you expect to solve during the project, if any?
 109
 110 The main challenge is one of communication. The majority of the technical
 111 development has been done thanks to NLnet
 112 but it was so complex and comprehensive that it risks overwhelming the ISA
 113 WG Members, whose primary driver has of course been IBM for the past 25
 114 years.
 115
 116 Libre-SOC proposes taking the Power ISA into mainstream computing,
 117 including Video Decode, 3D, GPU workloads, cryptography, and Desktop
 118 and Portable devices, all of which are far different from IBM's traditional
 119 Mainframe-style multi-billion-dollar Supercomputing business.
 120 We therefore have to be both deeply respectful of their achievements, and
 121 non-disruptive to their customer base, but
 122 also appropriately assertive now that the ISA is managed by the OpenPOWER
 123 Foundation.
 124
 125 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 126
 127 Partly covered above, Libre-SOC is exclusively FOSSHW and full transparency
 128 is paramount. That said we recognise that no FOSSHW team is going to
 129 manufacture FOSS ASICs in 7nm (unless several billion dollars is available
 130 to buy a Foundry and open up its PDK). To that end RED Semiconductor Ltd
 131 has been formed by us as an Independent Entity,
 132 which will commercialise Libre-SOC's designs and handle
 133 any Commercially-confidential matters that a Transparency-committed
 134 FOSSHW team simply
 135 cannot. Thus, RS will join the OpenPOWER Foundation and help ensure,
 136 from the "other side of the fence", that matters progress smoothly
 137 for IBM and other OPF Members.
 138
 139 RED Semiconductor Ltd will the commercial point of contact for Simple-V
 140 where Organisations are unable to deal with FOSS Entities. This maximises
 141 the broad market benefit of the technology, in line with European Objectives.
 142
 143 We are already set to submit presentations through multiple Conferences
 144 as has been ongoing since 2019 as can be seen at <https://libre-soc.org/conferences> and will continue to submit press releases to
 145 OPF <https://openpowerfoundation.org/blog/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/>. Our entire development is public
 146 so is accessible to all.
 147
 148 # Extra info to be submitted
 149
 150 the budget is high because we honestly do not know yet how much work
 151 IBM and the ISA WG expects us to do.  we do however know that there
 152 will be announcements very soon. If it turns out to be less work
 153 we are more than happy to go with a proportionately smaller budget.