vendor.xilinx_{7series,ultrascale}: don't use `write_verilog -decimal`.
[nmigen.git] / nmigen / __init__.py
1 import pkg_resources
2 try:
3 __version__ = pkg_resources.get_distribution(__name__).version
4 except pkg_resources.DistributionNotFound:
5 pass
6
7
8 from .hdl import *
9
10
11 __all__ = [
12 "Shape", "unsigned", "signed",
13 "Value", "Const", "C", "Mux", "Cat", "Repl", "Array", "Signal", "ClockSignal", "ResetSignal",
14 "Module",
15 "ClockDomain",
16 "Elaboratable", "Fragment", "Instance",
17 "Memory",
18 "Record",
19 "DomainRenamer", "ResetInserter", "EnableInserter",
20 ]