nmigen/back/pysim.py

   1 import math
   2 import inspect
   3 import warnings
   4 from contextlib import contextmanager
   5 from bitarray import bitarray
   6 from vcd import VCDWriter
   7 from vcd.gtkw import GTKWSave
   8
   9 from ..tools import flatten
  10 from ..hdl.ast import *
  11 from ..hdl.ir import *
  12 from ..hdl.xfrm import ValueVisitor, StatementVisitor
  13
  14
  15 __all__ = ["Simulator", "Delay", "Tick", "Passive", "DeadlineError"]
  16
  17
  18 class DeadlineError(Exception):
  19     pass
  20
  21
  22 class _State:
  23     __slots__ = ("curr", "curr_dirty", "next", "next_dirty")
  24
  25     def __init__(self):
  26         self.curr = []
  27         self.next = []
  28         self.curr_dirty = bitarray()
  29         self.next_dirty = bitarray()
  30
  31     def add(self, value):
  32         slot = len(self.curr)
  33         self.curr.append(value)
  34         self.next.append(value)
  35         self.curr_dirty.append(True)
  36         self.next_dirty.append(False)
  37         return slot
  38
  39     def set(self, slot, value):
  40         if self.next[slot] != value:
  41             self.next_dirty[slot] = True
  42             self.next[slot] = value
  43
  44     def commit(self, slot):
  45         old_value = self.curr[slot]
  46         new_value = self.next[slot]
  47         if old_value != new_value:
  48             self.next_dirty[slot] = False
  49             self.curr_dirty[slot] = True
  50             self.curr[slot] = new_value
  51         return old_value, new_value
  52
  53     def flush_curr_dirty(self):
  54         while True:
  55             try:
  56                 slot = self.curr_dirty.index(True)
  57             except ValueError:
  58                 break
  59             self.curr_dirty[slot] = False
  60             yield slot
  61
  62     def iter_next_dirty(self):
  63         start = 0
  64         while True:
  65             try:
  66                 slot  = self.next_dirty.index(True, start)
  67                 start = slot + 1
  68             except ValueError:
  69                 break
  70             yield slot
  71
  72
  73 normalize = Const.normalize
  74
  75
  76 class _ValueCompiler(ValueVisitor):
  77     def on_AnyConst(self, value):
  78         raise NotImplementedError # :nocov:
  79
  80     def on_AnySeq(self, value):
  81         raise NotImplementedError # :nocov:
  82
  83     def on_Sample(self, value):
  84         raise NotImplementedError # :nocov:
  85
  86     def on_Record(self, value):
  87         return self(Cat(value.fields.values()))
  88
  89
  90 class _RHSValueCompiler(_ValueCompiler):
  91     def __init__(self, signal_slots, sensitivity=None, mode="rhs"):
  92         self.signal_slots = signal_slots
  93         self.sensitivity  = sensitivity
  94         self.signal_mode  = mode
  95
  96     def on_Const(self, value):
  97         return lambda state: value.value
  98
  99     def on_Signal(self, value):
 100         if self.sensitivity is not None:
 101             self.sensitivity.add(value)
 102         if value not in self.signal_slots:
 103             # A signal that is neither driven nor a port always remains at its reset state.
 104             return lambda state: value.reset
 105         value_slot = self.signal_slots[value]
 106         if self.signal_mode == "rhs":
 107             return lambda state: state.curr[value_slot]
 108         elif self.signal_mode == "lhs":
 109             return lambda state: state.next[value_slot]
 110         else:
 111             raise ValueError # :nocov:
 112
 113     def on_ClockSignal(self, value):
 114         raise NotImplementedError # :nocov:
 115
 116     def on_ResetSignal(self, value):
 117         raise NotImplementedError # :nocov:
 118
 119     def on_Operator(self, value):
 120         shape = value.shape()
 121         if len(value.operands) == 1:
 122             arg, = map(self, value.operands)
 123             if value.op == "~":
 124                 return lambda state: normalize(~arg(state), shape)
 125             if value.op == "-":
 126                 return lambda state: normalize(-arg(state), shape)
 127             if value.op == "b":
 128                 return lambda state: normalize(bool(arg(state)), shape)
 129         elif len(value.operands) == 2:
 130             lhs, rhs = map(self, value.operands)
 131             if value.op == "+":
 132                 return lambda state: normalize(lhs(state) +  rhs(state), shape)
 133             if value.op == "-":
 134                 return lambda state: normalize(lhs(state) -  rhs(state), shape)
 135             if value.op == "*":
 136                 return lambda state: normalize(lhs(state) *  rhs(state), shape)
 137             if value.op == "&":
 138                 return lambda state: normalize(lhs(state) &  rhs(state), shape)
 139             if value.op == "|":
 140                 return lambda state: normalize(lhs(state) |  rhs(state), shape)
 141             if value.op == "^":
 142                 return lambda state: normalize(lhs(state) ^  rhs(state), shape)
 143             if value.op == "<<":
 144                 def sshl(lhs, rhs):
 145                     return lhs << rhs if rhs >= 0 else lhs >> -rhs
 146                 return lambda state: normalize(sshl(lhs(state), rhs(state)), shape)
 147             if value.op == ">>":
 148                 def sshr(lhs, rhs):
 149                     return lhs >> rhs if rhs >= 0 else lhs << -rhs
 150                 return lambda state: normalize(sshr(lhs(state), rhs(state)), shape)
 151             if value.op == "==":
 152                 return lambda state: normalize(lhs(state) == rhs(state), shape)
 153             if value.op == "!=":
 154                 return lambda state: normalize(lhs(state) != rhs(state), shape)
 155             if value.op == "<":
 156                 return lambda state: normalize(lhs(state) <  rhs(state), shape)
 157             if value.op == "<=":
 158                 return lambda state: normalize(lhs(state) <= rhs(state), shape)
 159             if value.op == ">":
 160                 return lambda state: normalize(lhs(state) >  rhs(state), shape)
 161             if value.op == ">=":
 162                 return lambda state: normalize(lhs(state) >= rhs(state), shape)
 163         elif len(value.operands) == 3:
 164             if value.op == "m":
 165                 sel, val1, val0 = map(self, value.operands)
 166                 return lambda state: val1(state) if sel(state) else val0(state)
 167         raise NotImplementedError("Operator '{}' not implemented".format(value.op)) # :nocov:
 168
 169     def on_Slice(self, value):
 170         shape = value.shape()
 171         arg   = self(value.value)
 172         shift = value.start
 173         mask  = (1 << (value.end - value.start)) - 1
 174         return lambda state: normalize((arg(state) >> shift) & mask, shape)
 175
 176     def on_Part(self, value):
 177         shape = value.shape()
 178         arg   = self(value.value)
 179         shift = self(value.offset)
 180         mask  = (1 << value.width) - 1
 181         return lambda state: normalize((arg(state) >> shift(state)) & mask, shape)
 182
 183     def on_Cat(self, value):
 184         shape  = value.shape()
 185         parts  = []
 186         offset = 0
 187         for opnd in value.parts:
 188             parts.append((offset, (1 << len(opnd)) - 1, self(opnd)))
 189             offset += len(opnd)
 190         def eval(state):
 191             result = 0
 192             for offset, mask, opnd in parts:
 193                 result |= (opnd(state) & mask) << offset
 194             return normalize(result, shape)
 195         return eval
 196
 197     def on_Repl(self, value):
 198         shape  = value.shape()
 199         offset = len(value.value)
 200         mask   = (1 << len(value.value)) - 1
 201         count  = value.count
 202         opnd   = self(value.value)
 203         def eval(state):
 204             result = 0
 205             for _ in range(count):
 206                 result <<= offset
 207                 result  |= opnd(state)
 208             return normalize(result, shape)
 209         return eval
 210
 211     def on_ArrayProxy(self, value):
 212         shape  = value.shape()
 213         elems  = list(map(self, value.elems))
 214         index  = self(value.index)
 215         def eval(state):
 216             index_value = index(state)
 217             if index_value >= len(elems):
 218                 index_value = len(elems) - 1
 219             return normalize(elems[index_value](state), shape)
 220         return eval
 221
 222
 223 class _LHSValueCompiler(_ValueCompiler):
 224     def __init__(self, signal_slots, rhs_compiler):
 225         self.signal_slots = signal_slots
 226         self.rhs_compiler = rhs_compiler
 227
 228     def on_Const(self, value):
 229         raise TypeError # :nocov:
 230
 231     def on_Signal(self, value):
 232         shape = value.shape()
 233         value_slot = self.signal_slots[value]
 234         def eval(state, rhs):
 235             state.set(value_slot, normalize(rhs, shape))
 236         return eval
 237
 238     def on_ClockSignal(self, value):
 239         raise NotImplementedError # :nocov:
 240
 241     def on_ResetSignal(self, value):
 242         raise NotImplementedError # :nocov:
 243
 244     def on_Operator(self, value):
 245         raise TypeError # :nocov:
 246
 247     def on_Slice(self, value):
 248         lhs_r = self.rhs_compiler(value.value)
 249         lhs_l = self(value.value)
 250         shift = value.start
 251         mask  = (1 << (value.end - value.start)) - 1
 252         def eval(state, rhs):
 253             lhs_value  = lhs_r(state)
 254             lhs_value &= ~(mask << shift)
 255             lhs_value |= (rhs & mask) << shift
 256             lhs_l(state, lhs_value)
 257         return eval
 258
 259     def on_Part(self, value):
 260         lhs_r = self.rhs_compiler(value.value)
 261         lhs_l = self(value.value)
 262         shift = self.rhs_compiler(value.offset)
 263         mask  = (1 << value.width) - 1
 264         def eval(state, rhs):
 265             lhs_value   = lhs_r(state)
 266             shift_value = shift(state)
 267             lhs_value  &= ~(mask << shift_value)
 268             lhs_value  |= (rhs & mask) << shift_value
 269             lhs_l(state, lhs_value)
 270         return eval
 271
 272     def on_Cat(self, value):
 273         parts  = []
 274         offset = 0
 275         for opnd in value.parts:
 276             parts.append((offset, (1 << len(opnd)) - 1, self(opnd)))
 277             offset += len(opnd)
 278         def eval(state, rhs):
 279             for offset, mask, opnd in parts:
 280                 opnd(state, (rhs >> offset) & mask)
 281         return eval
 282
 283     def on_Repl(self, value):
 284         raise TypeError # :nocov:
 285
 286     def on_ArrayProxy(self, value):
 287         elems = list(map(self, value.elems))
 288         index = self.rhs_compiler(value.index)
 289         def eval(state, rhs):
 290             index_value = index(state)
 291             if index_value >= len(elems):
 292                 index_value = len(elems) - 1
 293             elems[index_value](state, rhs)
 294         return eval
 295
 296
 297 class _StatementCompiler(StatementVisitor):
 298     def __init__(self, signal_slots):
 299         self.sensitivity   = SignalSet()
 300         self.rrhs_compiler = _RHSValueCompiler(signal_slots, self.sensitivity, mode="rhs")
 301         self.lrhs_compiler = _RHSValueCompiler(signal_slots, self.sensitivity, mode="lhs")
 302         self.lhs_compiler  = _LHSValueCompiler(signal_slots, self.lrhs_compiler)
 303
 304     def on_Assign(self, stmt):
 305         shape = stmt.lhs.shape()
 306         lhs   = self.lhs_compiler(stmt.lhs)
 307         rhs   = self.rrhs_compiler(stmt.rhs)
 308         def run(state):
 309             lhs(state, normalize(rhs(state), shape))
 310         return run
 311
 312     def on_Assert(self, stmt):
 313         raise NotImplementedError("Asserts not yet implemented for Simulator backend.") # :nocov:
 314
 315     def on_Assume(self, stmt):
 316         pass # :nocov:
 317
 318     def on_Switch(self, stmt):
 319         test  = self.rrhs_compiler(stmt.test)
 320         cases = []
 321         for value, stmts in stmt.cases.items():
 322             if "-" in value:
 323                 mask  = "".join("0" if b == "-" else "1" for b in value)
 324                 value = "".join("0" if b == "-" else  b  for b in value)
 325             else:
 326                 mask  = "1" * len(value)
 327             mask  = int(mask,  2)
 328             value = int(value, 2)
 329             def make_test(mask, value):
 330                 return lambda test: test & mask == value
 331             cases.append((make_test(mask, value), self.on_statements(stmts)))
 332         def run(state):
 333             test_value = test(state)
 334             for check, body in cases:
 335                 if check(test_value):
 336                     body(state)
 337                     return
 338         return run
 339
 340     def on_statements(self, stmts):
 341         stmts = [self.on_statement(stmt) for stmt in stmts]
 342         def run(state):
 343             for stmt in stmts:
 344                 stmt(state)
 345         return run
 346
 347
 348 class Simulator:
 349     def __init__(self, fragment, vcd_file=None, gtkw_file=None, traces=()):
 350         self._fragment        = fragment
 351
 352         self._signal_slots    = SignalDict()  # Signal -> int/slot
 353         self._slot_signals    = list()        # int/slot -> Signal
 354
 355         self._domains         = dict()        # str/domain -> ClockDomain
 356         self._domain_triggers = list()        # int/slot -> str/domain
 357
 358         self._signals         = SignalSet()   # {Signal}
 359         self._comb_signals    = bitarray()    # {Signal}
 360         self._sync_signals    = bitarray()    # {Signal}
 361         self._user_signals    = bitarray()    # {Signal}
 362         self._domain_signals  = dict()        # str/domain -> {Signal}
 363
 364         self._started         = False
 365         self._timestamp       = 0.
 366         self._delta           = 0.
 367         self._epsilon         = 1e-10
 368         self._fastest_clock   = self._epsilon
 369         self._state           = _State()
 370
 371         self._processes       = set()         # {process}
 372         self._process_loc     = dict()        # process -> str/loc
 373         self._passive         = set()         # {process}
 374         self._suspended       = set()         # {process}
 375         self._wait_deadline   = dict()        # process -> float/timestamp
 376         self._wait_tick       = dict()        # process -> str/domain
 377
 378         self._funclets        = list()        # int/slot -> set(lambda)
 379
 380         self._vcd_file        = vcd_file
 381         self._vcd_writer      = None
 382         self._vcd_signals     = list()        # int/slot -> set(vcd_signal)
 383         self._vcd_names       = list()        # int/slot -> str/name
 384         self._gtkw_file       = gtkw_file
 385         self._traces          = traces
 386
 387         self._run_called      = False
 388
 389         while not isinstance(self._fragment, Fragment):
 390             self._fragment = self._fragment.get_fragment(platform=None)
 391
 392     @staticmethod
 393     def _check_process(process):
 394         if inspect.isgeneratorfunction(process):
 395             process = process()
 396         if not inspect.isgenerator(process):
 397             raise TypeError("Cannot add a process '{!r}' because it is not a generator or "
 398                             "a generator function"
 399                             .format(process))
 400         return process
 401
 402     def _name_process(self, process):
 403         if process in self._process_loc:
 404             return self._process_loc[process]
 405         else:
 406             frame = process.gi_frame
 407             return "{}:{}".format(inspect.getfile(frame), inspect.getlineno(frame))
 408
 409     def add_process(self, process):
 410         process = self._check_process(process)
 411         self._processes.add(process)
 412
 413     def add_sync_process(self, process, domain="sync"):
 414         process = self._check_process(process)
 415         def sync_process():
 416             try:
 417                 result = None
 418                 while True:
 419                     self._process_loc[sync_process] = self._name_process(process)
 420                     cmd = process.send(result)
 421                     if cmd is None:
 422                         cmd = Tick(domain)
 423                     result = yield cmd
 424             except StopIteration:
 425                 pass
 426         sync_process = sync_process()
 427         self.add_process(sync_process)
 428
 429     def add_clock(self, period, phase=None, domain="sync"):
 430         if self._fastest_clock == self._epsilon or period < self._fastest_clock:
 431             self._fastest_clock = period
 432
 433         half_period = period / 2
 434         if phase is None:
 435             phase = half_period
 436         clk = self._domains[domain].clk
 437         def clk_process():
 438             yield Passive()
 439             yield Delay(phase)
 440             while True:
 441                 yield clk.eq(1)
 442                 yield Delay(half_period)
 443                 yield clk.eq(0)
 444                 yield Delay(half_period)
 445         self.add_process(clk_process)
 446
 447     def __enter__(self):
 448         if self._vcd_file:
 449             self._vcd_writer = VCDWriter(self._vcd_file, timescale="100 ps",
 450                                          comment="Generated by nMigen")
 451
 452         root_fragment = self._fragment.prepare()
 453         self._domains = root_fragment.domains
 454
 455         hierarchy = {}
 456         def add_fragment(fragment, scope=()):
 457             hierarchy[fragment] = scope
 458             for index, (subfragment, name) in enumerate(fragment.subfragments):
 459                 if name is None:
 460                     add_fragment(subfragment, (*scope, "#{}".format(index)))
 461                 else:
 462                     add_fragment(subfragment, (*scope, name))
 463         add_fragment(root_fragment, scope=("top",))
 464
 465         def add_signal(signal):
 466             if signal not in self._signals:
 467                 self._signals.add(signal)
 468
 469                 signal_slot = self._state.add(normalize(signal.reset, signal.shape()))
 470                 self._signal_slots[signal] = signal_slot
 471                 self._slot_signals.append(signal)
 472
 473                 self._comb_signals.append(False)
 474                 self._sync_signals.append(False)
 475                 self._user_signals.append(False)
 476                 for domain in self._domains:
 477                     if domain not in self._domain_signals:
 478                         self._domain_signals[domain] = bitarray()
 479                     self._domain_signals[domain].append(False)
 480
 481                 self._funclets.append(set())
 482
 483                 self._domain_triggers.append(None)
 484                 if self._vcd_writer:
 485                     self._vcd_signals.append(set())
 486                     self._vcd_names.append(None)
 487
 488             return self._signal_slots[signal]
 489
 490         def add_domain_signal(signal, domain):
 491             signal_slot = add_signal(signal)
 492             self._domain_triggers[signal_slot] = domain
 493
 494         for fragment, fragment_scope in hierarchy.items():
 495             for signal in fragment.iter_signals():
 496                 add_signal(signal)
 497
 498             for domain, cd in fragment.domains.items():
 499                 add_domain_signal(cd.clk, domain)
 500                 if cd.rst is not None:
 501                     add_domain_signal(cd.rst, domain)
 502
 503         for fragment, fragment_scope in hierarchy.items():
 504             for signal in fragment.iter_signals():
 505                 if not self._vcd_writer:
 506                     continue
 507
 508                 signal_slot = self._signal_slots[signal]
 509
 510                 for subfragment, name in fragment.subfragments:
 511                     if signal in subfragment.ports:
 512                         var_name = "{}_{}".format(name, signal.name)
 513                         break
 514                 else:
 515                     var_name = signal.name
 516
 517                 if signal.decoder:
 518                     var_type = "string"
 519                     var_size = 1
 520                     var_init = signal.decoder(signal.reset).replace(" ", "_")
 521                 else:
 522                     var_type = "wire"
 523                     var_size = signal.nbits
 524                     var_init = signal.reset
 525
 526                 suffix = None
 527                 while True:
 528                     try:
 529                         if suffix is None:
 530                             var_name_suffix = var_name
 531                         else:
 532                             var_name_suffix = "{}${}".format(var_name, suffix)
 533                         self._vcd_signals[signal_slot].add(self._vcd_writer.register_var(
 534                             scope=".".join(fragment_scope), name=var_name_suffix,
 535                             var_type=var_type, size=var_size, init=var_init))
 536                         if self._vcd_names[signal_slot] is None:
 537                             self._vcd_names[signal_slot] = \
 538                                 ".".join(fragment_scope + (var_name_suffix,))
 539                         break
 540                     except KeyError:
 541                         suffix = (suffix or 0) + 1
 542
 543             for domain, signals in fragment.drivers.items():
 544                 signals_bits = bitarray(len(self._signals))
 545                 signals_bits.setall(False)
 546                 for signal in signals:
 547                     signals_bits[self._signal_slots[signal]] = True
 548
 549                 if domain is None:
 550                     self._comb_signals |= signals_bits
 551                 else:
 552                     self._sync_signals |= signals_bits
 553                     self._domain_signals[domain] |= signals_bits
 554
 555             statements = []
 556             for signal in fragment.iter_comb():
 557                 statements.append(signal.eq(signal.reset))
 558             for domain, signal in fragment.iter_sync():
 559                 statements.append(signal.eq(signal))
 560             statements += fragment.statements
 561
 562             compiler = _StatementCompiler(self._signal_slots)
 563             funclet = compiler(statements)
 564
 565             def add_funclet(signal, funclet):
 566                 if signal in self._signal_slots:
 567                     self._funclets[self._signal_slots[signal]].add(funclet)
 568
 569             for signal in compiler.sensitivity:
 570                 add_funclet(signal, funclet)
 571             for domain, cd in fragment.domains.items():
 572                 add_funclet(cd.clk, funclet)
 573                 if cd.rst is not None:
 574                     add_funclet(cd.rst, funclet)
 575
 576         self._user_signals = bitarray(len(self._signals))
 577         self._user_signals.setall(True)
 578         self._user_signals &= ~self._comb_signals
 579         self._user_signals &= ~self._sync_signals
 580
 581         return self
 582
 583     def _update_dirty_signals(self):
 584         """Perform the statement part of IR processes (aka RTLIL case)."""
 585         # First, for all dirty signals, use sensitivity lists to determine the set of fragments
 586         # that need their statements to be reevaluated because the signals changed at the previous
 587         # delta cycle.
 588         funclets = set()
 589         for signal_slot in self._state.flush_curr_dirty():
 590             funclets.update(self._funclets[signal_slot])
 591
 592         # Second, compute the values of all signals at the start of the next delta cycle, by
 593         # running precompiled statements.
 594         for funclet in funclets:
 595             funclet(self._state)
 596
 597     def _commit_signal(self, signal_slot, domains):
 598         """Perform the driver part of IR processes (aka RTLIL sync), for individual signals."""
 599         # Take the computed value (at the start of this delta cycle) of a signal (that could have
 600         # come from an IR process that ran earlier, or modified by a simulator process) and update
 601         # the value for this delta cycle.
 602         old, new = self._state.commit(signal_slot)
 603         if old == new:
 604             return
 605
 606         # If the signal is a clock that triggers synchronous logic, record that fact.
 607         if new == 1 and self._domain_triggers[signal_slot] is not None:
 608             domains.add(self._domain_triggers[signal_slot])
 609
 610         if self._vcd_writer:
 611             # Finally, dump the new value to the VCD file.
 612             for vcd_signal in self._vcd_signals[signal_slot]:
 613                 signal = self._slot_signals[signal_slot]
 614                 if signal.decoder:
 615                     var_value = signal.decoder(new).replace(" ", "_")
 616                 else:
 617                     var_value = new
 618                 vcd_timestamp = (self._timestamp + self._delta) / self._epsilon
 619                 self._vcd_writer.change(vcd_signal, vcd_timestamp, var_value)
 620
 621     def _commit_comb_signals(self, domains):
 622         """Perform the comb part of IR processes (aka RTLIL always)."""
 623         # Take the computed value (at the start of this delta cycle) of every comb signal and
 624         # update the value for this delta cycle.
 625         for signal_slot in self._state.iter_next_dirty():
 626             if self._comb_signals[signal_slot]:
 627                 self._commit_signal(signal_slot, domains)
 628
 629     def _commit_sync_signals(self, domains):
 630         """Perform the sync part of IR processes (aka RTLIL posedge)."""
 631         # At entry, `domains` contains a list of every simultaneously triggered sync update.
 632         while domains:
 633             # Advance the timeline a bit (purely for observational purposes) and commit all of them
 634             # at the same timestamp.
 635             self._delta += self._epsilon
 636             curr_domains, domains = domains, set()
 637
 638             while curr_domains:
 639                 domain = curr_domains.pop()
 640
 641                 # Wake up any simulator processes that wait for a domain tick.
 642                 for process, wait_domain in list(self._wait_tick.items()):
 643                     if domain == wait_domain:
 644                         del self._wait_tick[process]
 645                         self._suspended.remove(process)
 646
 647                         # Immediately run the process. It is important that this happens here,
 648                         # and not on the next step, when all the processes will run anyway,
 649                         # because Tick() simulates an edge triggered process. Like DFFs that latch
 650                         # a value from the previous clock cycle, simulator processes observe signal
 651                         # values from the previous clock cycle on a tick, too.
 652                         self._run_process(process)
 653
 654                 # Take the computed value (at the start of this delta cycle) of every sync signal
 655                 # in this domain and update the value for this delta cycle. This can trigger more
 656                 # synchronous logic, so record that.
 657                 for signal_slot in self._state.iter_next_dirty():
 658                     if self._domain_signals[domain][signal_slot]:
 659                         self._commit_signal(signal_slot, domains)
 660
 661             # Unless handling synchronous logic above has triggered more synchronous logic (which
 662             # can happen e.g. if a domain is clocked off a clock divisor in fabric), we're done.
 663             # Otherwise, do one more round of updates.
 664
 665     def _run_process(self, process):
 666         try:
 667             cmd = process.send(None)
 668             while True:
 669                 if type(cmd) is Delay:
 670                     if cmd.interval is None:
 671                         interval = self._epsilon
 672                     else:
 673                         interval = cmd.interval
 674                     self._wait_deadline[process] = self._timestamp + interval
 675                     self._suspended.add(process)
 676                     break
 677
 678                 elif type(cmd) is Tick:
 679                     self._wait_tick[process] = cmd.domain
 680                     self._suspended.add(process)
 681                     break
 682
 683                 elif type(cmd) is Passive:
 684                     self._passive.add(process)
 685
 686                 elif type(cmd) is Assign:
 687                     lhs_signals = cmd.lhs._lhs_signals()
 688                     for signal in lhs_signals:
 689                         if not signal in self._signals:
 690                             raise ValueError("Process '{}' sent a request to set signal '{!r}', "
 691                                              "which is not a part of simulation"
 692                                              .format(self._name_process(process), signal))
 693                         signal_slot = self._signal_slots[signal]
 694                         if self._comb_signals[signal_slot]:
 695                             raise ValueError("Process '{}' sent a request to set signal '{!r}', "
 696                                              "which is a part of combinatorial assignment in "
 697                                              "simulation"
 698                                              .format(self._name_process(process), signal))
 699
 700                     if type(cmd.lhs) is Signal and type(cmd.rhs) is Const:
 701                         # Fast path.
 702                         self._state.set(self._signal_slots[cmd.lhs],
 703                                         normalize(cmd.rhs.value, cmd.lhs.shape()))
 704                     else:
 705                         compiler = _StatementCompiler(self._signal_slots)
 706                         funclet = compiler(cmd)
 707                         funclet(self._state)
 708
 709                     domains = set()
 710                     for signal in lhs_signals:
 711                         self._commit_signal(self._signal_slots[signal], domains)
 712                     self._commit_sync_signals(domains)
 713
 714                 elif type(cmd) is Signal:
 715                     # Fast path.
 716                     cmd = process.send(self._state.curr[self._signal_slots[cmd]])
 717                     continue
 718
 719                 elif isinstance(cmd, Value):
 720                     compiler = _RHSValueCompiler(self._signal_slots)
 721                     funclet = compiler(cmd)
 722                     cmd = process.send(funclet(self._state))
 723                     continue
 724
 725                 else:
 726                     raise TypeError("Received unsupported command '{!r}' from process '{}'"
 727                                     .format(cmd, self._name_process(process)))
 728
 729                 cmd = process.send(None)
 730
 731         except StopIteration:
 732             self._processes.remove(process)
 733             self._passive.discard(process)
 734
 735         except Exception as e:
 736             process.throw(e)
 737
 738     def step(self, run_passive=False):
 739         # Are there any delta cycles we should run?
 740         if self._state.curr_dirty.any():
 741             # We might run some delta cycles, and we have simulator processes waiting on
 742             # a deadline. Take care to not exceed the closest deadline.
 743             if self._wait_deadline and \
 744                     (self._timestamp + self._delta) >= min(self._wait_deadline.values()):
 745                 # Oops, we blew the deadline. We *could* run the processes now, but this is
 746                 # virtually certainly a logic loop and a design bug, so bail out instead.d
 747                 raise DeadlineError("Delta cycles exceeded process deadline; combinatorial loop?")
 748
 749             domains = set()
 750             while self._state.curr_dirty.any():
 751                 self._update_dirty_signals()
 752                 self._commit_comb_signals(domains)
 753             self._commit_sync_signals(domains)
 754             return True
 755
 756         # Are there any processes that haven't had a chance to run yet?
 757         if len(self._processes) > len(self._suspended):
 758             # Schedule an arbitrary one.
 759             process = (self._processes - set(self._suspended)).pop()
 760             self._run_process(process)
 761             return True
 762
 763         # All processes are suspended. Are any of them active?
 764         if len(self._processes) > len(self._passive) or run_passive:
 765             # Are any of them suspended before a deadline?
 766             if self._wait_deadline:
 767                 # Schedule the one with the lowest deadline.
 768                 process, deadline = min(self._wait_deadline.items(), key=lambda x: x[1])
 769                 del self._wait_deadline[process]
 770                 self._suspended.remove(process)
 771                 self._timestamp = deadline
 772                 self._delta = 0.
 773                 self._run_process(process)
 774                 return True
 775
 776         # No processes, or all processes are passive. Nothing to do!
 777         return False
 778
 779     def run(self):
 780         self._run_called = True
 781
 782         while self.step():
 783             pass
 784
 785     def run_until(self, deadline, run_passive=False):
 786         self._run_called = True
 787
 788         while self._timestamp < deadline:
 789             if not self.step(run_passive):
 790                 return False
 791
 792         return True
 793
 794     def __exit__(self, *args):
 795         if not self._run_called:
 796             warnings.warn("Simulation created, but not run", UserWarning)
 797
 798         if self._vcd_writer:
 799             vcd_timestamp = (self._timestamp + self._delta) / self._epsilon
 800             self._vcd_writer.close(vcd_timestamp)
 801
 802         if self._vcd_file and self._gtkw_file:
 803             gtkw_save = GTKWSave(self._gtkw_file)
 804             if hasattr(self._vcd_file, "name"):
 805                 gtkw_save.dumpfile(self._vcd_file.name)
 806             if hasattr(self._vcd_file, "tell"):
 807                 gtkw_save.dumpfile_size(self._vcd_file.tell())
 808
 809             gtkw_save.treeopen("top")
 810             gtkw_save.zoom_markers(math.log(self._epsilon / self._fastest_clock) - 14)
 811
 812             def add_trace(signal, **kwargs):
 813                 signal_slot = self._signal_slots[signal]
 814                 if self._vcd_names[signal_slot] is not None:
 815                     if len(signal) > 1:
 816                         suffix = "[{}:0]".format(len(signal) - 1)
 817                     else:
 818                         suffix = ""
 819                     gtkw_save.trace(self._vcd_names[signal_slot] + suffix, **kwargs)
 820
 821             for domain, cd in self._domains.items():
 822                 with gtkw_save.group("d.{}".format(domain)):
 823                     if cd.rst is not None:
 824                         add_trace(cd.rst)
 825                     add_trace(cd.clk)
 826
 827             for signal in self._traces:
 828                 add_trace(signal)
 829
 830         if self._vcd_file:
 831             self._vcd_file.close()
 832         if self._gtkw_file:
 833             self._gtkw_file.close()