nmigen/back/pysim.py

   1 import math
   2 import inspect
   3 from contextlib import contextmanager
   4 from vcd import VCDWriter
   5 from vcd.gtkw import GTKWSave
   6
   7 from ..tools import flatten
   8 from ..hdl.ast import *
   9 from ..hdl.xfrm import ValueTransformer, StatementTransformer
  10
  11
  12 __all__ = ["Simulator", "Delay", "Tick", "Passive", "DeadlineError"]
  13
  14
  15 class DeadlineError(Exception):
  16     pass
  17
  18
  19 class _State:
  20     __slots__ = ("curr", "curr_dirty", "next", "next_dirty")
  21
  22     def __init__(self):
  23         self.curr = ValueDict()
  24         self.next = ValueDict()
  25         self.curr_dirty = ValueSet()
  26         self.next_dirty = ValueSet()
  27
  28     def set(self, signal, value):
  29         assert isinstance(value, int)
  30         if self.next[signal] != value:
  31             self.next_dirty.add(signal)
  32             self.next[signal] = value
  33
  34     def commit(self, signal):
  35         old_value = self.curr[signal]
  36         new_value = self.next[signal]
  37         if old_value != new_value:
  38             self.next_dirty.remove(signal)
  39             self.curr_dirty.add(signal)
  40             self.curr[signal] = new_value
  41         return old_value, new_value
  42
  43
  44 normalize = Const.normalize
  45
  46
  47 class _RHSValueCompiler(ValueTransformer):
  48     def __init__(self, sensitivity=None):
  49         self.sensitivity = sensitivity
  50
  51     def on_Const(self, value):
  52         return lambda state: value.value
  53
  54     def on_Signal(self, value):
  55         if self.sensitivity is not None:
  56             self.sensitivity.add(value)
  57         return lambda state: state.curr[value]
  58
  59     def on_ClockSignal(self, value):
  60         raise NotImplementedError # :nocov:
  61
  62     def on_ResetSignal(self, value):
  63         raise NotImplementedError # :nocov:
  64
  65     def on_Operator(self, value):
  66         shape = value.shape()
  67         if len(value.operands) == 1:
  68             arg, = map(self, value.operands)
  69             if value.op == "~":
  70                 return lambda state: normalize(~arg(state), shape)
  71             if value.op == "-":
  72                 return lambda state: normalize(-arg(state), shape)
  73             if value.op == "b":
  74                 return lambda state: normalize(bool(arg(state)), shape)
  75         elif len(value.operands) == 2:
  76             lhs, rhs = map(self, value.operands)
  77             if value.op == "+":
  78                 return lambda state: normalize(lhs(state) +  rhs(state), shape)
  79             if value.op == "-":
  80                 return lambda state: normalize(lhs(state) -  rhs(state), shape)
  81             if value.op == "&":
  82                 return lambda state: normalize(lhs(state) &  rhs(state), shape)
  83             if value.op == "|":
  84                 return lambda state: normalize(lhs(state) |  rhs(state), shape)
  85             if value.op == "^":
  86                 return lambda state: normalize(lhs(state) ^  rhs(state), shape)
  87             if value.op == "<<":
  88                 def sshl(lhs, rhs):
  89                     return lhs << rhs if rhs >= 0 else lhs >> -rhs
  90                 return lambda state: normalize(sshl(lhs(state), rhs(state)), shape)
  91             if value.op == ">>":
  92                 def sshr(lhs, rhs):
  93                     return lhs >> rhs if rhs >= 0 else lhs << -rhs
  94                 return lambda state: normalize(sshr(lhs(state), rhs(state)), shape)
  95             if value.op == "==":
  96                 return lambda state: normalize(lhs(state) == rhs(state), shape)
  97             if value.op == "!=":
  98                 return lambda state: normalize(lhs(state) != rhs(state), shape)
  99             if value.op == "<":
 100                 return lambda state: normalize(lhs(state) <  rhs(state), shape)
 101             if value.op == "<=":
 102                 return lambda state: normalize(lhs(state) <= rhs(state), shape)
 103             if value.op == ">":
 104                 return lambda state: normalize(lhs(state) >  rhs(state), shape)
 105             if value.op == ">=":
 106                 return lambda state: normalize(lhs(state) >= rhs(state), shape)
 107         elif len(value.operands) == 3:
 108             if value.op == "m":
 109                 sel, val1, val0 = map(self, value.operands)
 110                 return lambda state: val1(state) if sel(state) else val0(state)
 111         raise NotImplementedError("Operator '{}' not implemented".format(value.op)) # :nocov:
 112
 113     def on_Slice(self, value):
 114         shape = value.shape()
 115         arg   = self(value.value)
 116         shift = value.start
 117         mask  = (1 << (value.end - value.start)) - 1
 118         return lambda state: normalize((arg(state) >> shift) & mask, shape)
 119
 120     def on_Part(self, value):
 121         raise NotImplementedError
 122
 123     def on_Cat(self, value):
 124         shape  = value.shape()
 125         parts  = []
 126         offset = 0
 127         for opnd in value.operands:
 128             parts.append((offset, (1 << len(opnd)) - 1, self(opnd)))
 129             offset += len(opnd)
 130         def eval(state):
 131             result = 0
 132             for offset, mask, opnd in parts:
 133                 result |= (opnd(state) & mask) << offset
 134             return normalize(result, shape)
 135         return eval
 136
 137     def on_Repl(self, value):
 138         shape  = value.shape()
 139         offset = len(value.value)
 140         mask   = (1 << len(value.value)) - 1
 141         count  = value.count
 142         opnd   = self(value.value)
 143         def eval(state):
 144             result = 0
 145             for _ in range(count):
 146                 result <<= offset
 147                 result  |= opnd(state)
 148             return normalize(result, shape)
 149         return eval
 150
 151
 152 class _StatementCompiler(StatementTransformer):
 153     def __init__(self):
 154         self.sensitivity  = ValueSet()
 155         self.rhs_compiler = _RHSValueCompiler(self.sensitivity)
 156
 157     def lhs_compiler(self, value):
 158         # TODO
 159         return lambda state, arg: state.set(value, arg)
 160
 161     def on_Assign(self, stmt):
 162         assert isinstance(stmt.lhs, Signal)
 163         shape = stmt.lhs.shape()
 164         lhs   = self.lhs_compiler(stmt.lhs)
 165         rhs   = self.rhs_compiler(stmt.rhs)
 166         def run(state):
 167             lhs(state, normalize(rhs(state), shape))
 168         return run
 169
 170     def on_Switch(self, stmt):
 171         test  = self.rhs_compiler(stmt.test)
 172         cases = []
 173         for value, stmts in stmt.cases.items():
 174             if "-" in value:
 175                 mask  = "".join("0" if b == "-" else "1" for b in value)
 176                 value = "".join("0" if b == "-" else  b  for b in value)
 177             else:
 178                 mask  = "1" * len(value)
 179             mask  = int(mask,  2)
 180             value = int(value, 2)
 181             def make_test(mask, value):
 182                 return lambda test: test & mask == value
 183             cases.append((make_test(mask, value), self.on_statements(stmts)))
 184         def run(state):
 185             test_value = test(state)
 186             for check, body in cases:
 187                 if check(test_value):
 188                     body(state)
 189                     return
 190         return run
 191
 192     def on_statements(self, stmts):
 193         stmts = [self.on_statement(stmt) for stmt in stmts]
 194         def run(state):
 195             for stmt in stmts:
 196                 stmt(state)
 197         return run
 198
 199
 200 class Simulator:
 201     def __init__(self, fragment, vcd_file=None, gtkw_file=None, traces=()):
 202         self._fragment        = fragment
 203
 204         self._domains         = dict()        # str/domain -> ClockDomain
 205         self._domain_triggers = ValueDict()   # Signal -> str/domain
 206         self._domain_signals  = dict()        # str/domain -> {Signal}
 207
 208         self._signals         = ValueSet()    # {Signal}
 209         self._comb_signals    = ValueSet()    # {Signal}
 210         self._sync_signals    = ValueSet()    # {Signal}
 211         self._user_signals    = ValueSet()    # {Signal}
 212
 213         self._started         = False
 214         self._timestamp       = 0.
 215         self._delta           = 0.
 216         self._epsilon         = 1e-10
 217         self._fastest_clock   = self._epsilon
 218         self._state           = _State()
 219
 220         self._processes       = set()         # {process}
 221         self._process_loc     = dict()        # process -> str/loc
 222         self._passive         = set()         # {process}
 223         self._suspended       = set()         # {process}
 224         self._wait_deadline   = dict()        # process -> float/timestamp
 225         self._wait_tick       = dict()        # process -> str/domain
 226
 227         self._funclets        = ValueDict()   # Signal -> set(lambda)
 228
 229         self._vcd_file        = vcd_file
 230         self._vcd_writer      = None
 231         self._vcd_signals     = ValueDict()   # signal -> set(vcd_signal)
 232         self._vcd_names       = ValueDict()   # signal -> str/name
 233         self._gtkw_file       = gtkw_file
 234         self._traces          = traces
 235
 236     @staticmethod
 237     def _check_process(process):
 238         if inspect.isgeneratorfunction(process):
 239             process = process()
 240         if not inspect.isgenerator(process):
 241             raise TypeError("Cannot add a process '{!r}' because it is not a generator or"
 242                             "a generator function"
 243                             .format(process))
 244         return process
 245
 246     def _name_process(self, process):
 247         if process in self._process_loc:
 248             return self._process_loc[process]
 249         else:
 250             frame = process.gi_frame
 251             return "{}:{}".format(inspect.getfile(frame), inspect.getlineno(frame))
 252
 253     def add_process(self, process):
 254         process = self._check_process(process)
 255         self._processes.add(process)
 256
 257     def add_sync_process(self, process, domain="sync"):
 258         process = self._check_process(process)
 259         def sync_process():
 260             try:
 261                 result = None
 262                 while True:
 263                     if result is None:
 264                         result = Tick(domain)
 265                     self._process_loc[sync_process] = self._name_process(process)
 266                     result = process.send((yield result))
 267             except StopIteration:
 268                 pass
 269         sync_process = sync_process()
 270         self.add_process(sync_process)
 271
 272     def add_clock(self, period, phase=None, domain="sync"):
 273         if self._fastest_clock == self._epsilon or period < self._fastest_clock:
 274             self._fastest_clock = period
 275
 276         half_period = period / 2
 277         if phase is None:
 278             phase = half_period
 279         clk = self._domains[domain].clk
 280         def clk_process():
 281             yield Passive()
 282             yield Delay(phase)
 283             while True:
 284                 yield clk.eq(1)
 285                 yield Delay(half_period)
 286                 yield clk.eq(0)
 287                 yield Delay(half_period)
 288         self.add_process(clk_process)
 289
 290     def __enter__(self):
 291         if self._vcd_file:
 292             self._vcd_writer = VCDWriter(self._vcd_file, timescale="100 ps",
 293                                          comment="Generated by nMigen")
 294
 295         root_fragment = self._fragment.prepare()
 296
 297         self._domains = root_fragment.domains
 298         for domain, cd in self._domains.items():
 299             self._domain_triggers[cd.clk] = domain
 300             if cd.rst is not None:
 301                 self._domain_triggers[cd.rst] = domain
 302             self._domain_signals[domain] = ValueSet()
 303
 304         hierarchy = {}
 305         def add_fragment(fragment, scope=()):
 306             hierarchy[fragment] = scope
 307             for subfragment, name in fragment.subfragments:
 308                 add_fragment(subfragment, (*scope, name))
 309         add_fragment(root_fragment)
 310
 311         for fragment, fragment_scope in hierarchy.items():
 312             for signal in fragment.iter_signals():
 313                 self._signals.add(signal)
 314
 315                 self._state.curr[signal] = self._state.next[signal] = \
 316                     normalize(signal.reset, signal.shape())
 317                 self._state.curr_dirty.add(signal)
 318
 319                 if not self._vcd_writer:
 320                     continue
 321
 322                 if signal not in self._vcd_signals:
 323                     self._vcd_signals[signal] = set()
 324
 325                 for subfragment, name in fragment.subfragments:
 326                     if signal in subfragment.ports:
 327                         var_name = "{}_{}".format(name, signal.name)
 328                         break
 329                 else:
 330                     var_name = signal.name
 331
 332                 if signal.decoder:
 333                     var_type = "string"
 334                     var_size = 1
 335                     var_init = signal.decoder(signal.reset).replace(" ", "_")
 336                 else:
 337                     var_type = "wire"
 338                     var_size = signal.nbits
 339                     var_init = signal.reset
 340
 341                 suffix = None
 342                 while True:
 343                     try:
 344                         if suffix is None:
 345                             var_name_suffix = var_name
 346                         else:
 347                             var_name_suffix = "{}${}".format(var_name, suffix)
 348                         self._vcd_signals[signal].add(self._vcd_writer.register_var(
 349                             scope=".".join(fragment_scope), name=var_name_suffix,
 350                             var_type=var_type, size=var_size, init=var_init))
 351                         if signal not in self._vcd_names:
 352                             self._vcd_names[signal] = ".".join(fragment_scope + (var_name_suffix,))
 353                         break
 354                     except KeyError:
 355                         suffix = (suffix or 0) + 1
 356
 357             for domain, signals in fragment.drivers.items():
 358                 if domain is None:
 359                     self._comb_signals.update(signals)
 360                 else:
 361                     self._sync_signals.update(signals)
 362                     self._domain_signals[domain].update(signals)
 363
 364             statements = []
 365             for signal in fragment.iter_comb():
 366                 statements.append(signal.eq(signal.reset))
 367             for domain, signal in fragment.iter_sync():
 368                 statements.append(signal.eq(signal))
 369             statements += fragment.statements
 370
 371             compiler = _StatementCompiler()
 372             funclet = compiler(statements)
 373
 374             def add_funclet(signal, funclet):
 375                 if signal not in self._funclets:
 376                     self._funclets[signal] = set()
 377                 self._funclets[signal].add(funclet)
 378
 379             for signal in compiler.sensitivity:
 380                 add_funclet(signal, funclet)
 381             for domain, cd in fragment.domains.items():
 382                 add_funclet(cd.clk, funclet)
 383                 if cd.rst is not None:
 384                     add_funclet(cd.rst, funclet)
 385
 386         self._user_signals = self._signals - self._comb_signals - self._sync_signals
 387
 388         return self
 389
 390     def _update_dirty_signals(self):
 391         """Perform the statement part of IR processes (aka RTLIL case)."""
 392         # First, for all dirty signals, use sensitivity lists to determine the set of fragments
 393         # that need their statements to be reevaluated because the signals changed at the previous
 394         # delta cycle.
 395         funclets = set()
 396         while self._state.curr_dirty:
 397             signal = self._state.curr_dirty.pop()
 398             if signal in self._funclets:
 399                 funclets.update(self._funclets[signal])
 400
 401         # Second, compute the values of all signals at the start of the next delta cycle, by
 402         # running precompiled statements.
 403         for funclet in funclets:
 404             funclet(self._state)
 405
 406     def _commit_signal(self, signal, domains):
 407         """Perform the driver part of IR processes (aka RTLIL sync), for individual signals."""
 408         # Take the computed value (at the start of this delta cycle) of a signal (that could have
 409         # come from an IR process that ran earlier, or modified by a simulator process) and update
 410         # the value for this delta cycle.
 411         old, new = self._state.commit(signal)
 412
 413         # If the signal is a clock that triggers synchronous logic, record that fact.
 414         if (old, new) == (0, 1) and signal in self._domain_triggers:
 415             domains.add(self._domain_triggers[signal])
 416
 417         if self._vcd_writer and old != new:
 418             # Finally, dump the new value to the VCD file.
 419             for vcd_signal in self._vcd_signals[signal]:
 420                 if signal.decoder:
 421                     var_value = signal.decoder(new).replace(" ", "_")
 422                 else:
 423                     var_value = new
 424                 vcd_timestamp = (self._timestamp + self._delta) / self._epsilon
 425                 self._vcd_writer.change(vcd_signal, vcd_timestamp, var_value)
 426
 427     def _commit_comb_signals(self, domains):
 428         """Perform the comb part of IR processes (aka RTLIL always)."""
 429         # Take the computed value (at the start of this delta cycle) of every comb signal and
 430         # update the value for this delta cycle.
 431         for signal in self._state.next_dirty:
 432             if signal in self._comb_signals:
 433                 self._commit_signal(signal, domains)
 434
 435     def _commit_sync_signals(self, domains):
 436         """Perform the sync part of IR processes (aka RTLIL posedge)."""
 437         # At entry, `domains` contains a list of every simultaneously triggered sync update.
 438         while domains:
 439             # Advance the timeline a bit (purely for observational purposes) and commit all of them
 440             # at the same timestamp.
 441             self._delta += self._epsilon
 442             curr_domains, domains = domains, set()
 443
 444             while curr_domains:
 445                 domain = curr_domains.pop()
 446
 447                 # Take the computed value (at the start of this delta cycle) of every sync signal
 448                 # in this domain and update the value for this delta cycle. This can trigger more
 449                 # synchronous logic, so record that.
 450                 for signal in self._state.next_dirty:
 451                     if signal in self._domain_signals[domain]:
 452                         self._commit_signal(signal, domains)
 453
 454                 # Wake up any simulator processes that wait for a domain tick.
 455                 for process, wait_domain in list(self._wait_tick.items()):
 456                     if domain == wait_domain:
 457                         del self._wait_tick[process]
 458                         self._suspended.remove(process)
 459
 460             # Unless handling synchronous logic above has triggered more synchronous logic (which
 461             # can happen e.g. if a domain is clocked off a clock divisor in fabric), we're done.
 462             # Otherwise, do one more round of updates.
 463
 464     def _run_process(self, process):
 465         try:
 466             cmd = process.send(None)
 467             while True:
 468                 if isinstance(cmd, Delay):
 469                     if cmd.interval is None:
 470                         interval = self._epsilon
 471                     else:
 472                         interval = cmd.interval
 473                     self._wait_deadline[process] = self._timestamp + interval
 474                     self._suspended.add(process)
 475
 476                 elif isinstance(cmd, Tick):
 477                     self._wait_tick[process] = cmd.domain
 478                     self._suspended.add(process)
 479
 480                 elif isinstance(cmd, Passive):
 481                     self._passive.add(process)
 482
 483                 elif isinstance(cmd, Value):
 484                     compiler = _RHSValueCompiler()
 485                     funclet = compiler(cmd)
 486                     cmd = process.send(funclet(self._state))
 487                     continue
 488
 489                 elif isinstance(cmd, Assign):
 490                     lhs_signals = cmd.lhs._lhs_signals()
 491                     for signal in lhs_signals:
 492                         if not signal in self._signals:
 493                             raise ValueError("Process '{}' sent a request to set signal '{!r}', "
 494                                              "which is not a part of simulation"
 495                                              .format(self._name_process(process), signal))
 496                         if signal in self._comb_signals:
 497                             raise ValueError("Process '{}' sent a request to set signal '{!r}', "
 498                                              "which is a part of combinatorial assignment in "
 499                                              "simulation"
 500                                              .format(self._name_process(process), signal))
 501
 502                     compiler = _StatementCompiler()
 503                     funclet = compiler(cmd)
 504                     funclet(self._state)
 505
 506                     domains = set()
 507                     for signal in lhs_signals:
 508                         self._commit_signal(signal, domains)
 509                     self._commit_sync_signals(domains)
 510
 511                 else:
 512                     raise TypeError("Received unsupported command '{!r}' from process '{}'"
 513                                     .format(cmd, self._name_process(process)))
 514
 515                 break
 516
 517         except StopIteration:
 518             self._processes.remove(process)
 519             self._passive.discard(process)
 520
 521         except Exception as e:
 522             process.throw(e)
 523
 524     def step(self, run_passive=False):
 525         # Are there any delta cycles we should run?
 526         if self._state.curr_dirty:
 527             # We might run some delta cycles, and we have simulator processes waiting on
 528             # a deadline. Take care to not exceed the closest deadline.
 529             if self._wait_deadline and \
 530                     (self._timestamp + self._delta) >= min(self._wait_deadline.values()):
 531                 # Oops, we blew the deadline. We *could* run the processes now, but this is
 532                 # virtually certainly a logic loop and a design bug, so bail out instead.d
 533                 raise DeadlineError("Delta cycles exceeded process deadline; combinatorial loop?")
 534
 535             domains = set()
 536             while self._state.curr_dirty:
 537                 self._update_dirty_signals()
 538                 self._commit_comb_signals(domains)
 539             self._commit_sync_signals(domains)
 540             return True
 541
 542         # Are there any processes that haven't had a chance to run yet?
 543         if len(self._processes) > len(self._suspended):
 544             # Schedule an arbitrary one.
 545             process = (self._processes - set(self._suspended)).pop()
 546             self._run_process(process)
 547             return True
 548
 549         # All processes are suspended. Are any of them active?
 550         if len(self._processes) > len(self._passive) or run_passive:
 551             # Are any of them suspended before a deadline?
 552             if self._wait_deadline:
 553                 # Schedule the one with the lowest deadline.
 554                 process, deadline = min(self._wait_deadline.items(), key=lambda x: x[1])
 555                 del self._wait_deadline[process]
 556                 self._suspended.remove(process)
 557                 self._timestamp = deadline
 558                 self._delta = 0.
 559                 self._run_process(process)
 560                 return True
 561
 562         # No processes, or all processes are passive. Nothing to do!
 563         return False
 564
 565     def run(self):
 566         while self.step():
 567             pass
 568
 569     def run_until(self, deadline, run_passive=False):
 570         while self._timestamp < deadline:
 571             if not self.step(run_passive):
 572                 return False
 573
 574         return True
 575
 576     def __exit__(self, *args):
 577         if self._vcd_writer:
 578             vcd_timestamp = (self._timestamp + self._delta) / self._epsilon
 579             self._vcd_writer.close(vcd_timestamp)
 580
 581         if self._vcd_file and self._gtkw_file:
 582             gtkw_save = GTKWSave(self._gtkw_file)
 583             if hasattr(self._vcd_file, "name"):
 584                 gtkw_save.dumpfile(self._vcd_file.name)
 585             if hasattr(self._vcd_file, "tell"):
 586                 gtkw_save.dumpfile_size(self._vcd_file.tell())
 587
 588             gtkw_save.treeopen("top")
 589             gtkw_save.zoom_markers(math.log(self._epsilon / self._fastest_clock) - 14)
 590
 591             def add_trace(signal, **kwargs):
 592                 if signal in self._vcd_names:
 593                     if len(signal) > 1:
 594                         suffix = "[{}:0]".format(len(signal) - 1)
 595                     else:
 596                         suffix = ""
 597                     gtkw_save.trace(self._vcd_names[signal] + suffix, **kwargs)
 598
 599             for domain, cd in self._domains.items():
 600                 with gtkw_save.group("d.{}".format(domain)):
 601                     if cd.rst is not None:
 602                         add_trace(cd.rst)
 603                     add_trace(cd.clk)
 604
 605             for signal in self._traces:
 606                 add_trace(signal)
 607
 608         if self._vcd_file:
 609             self._vcd_file.close()
 610         if self._gtkw_file:
 611             self._gtkw_file.close()