nmigen/cli.py

   1 import argparse
   2
   3 from .back import rtlil, verilog, pysim
   4
   5
   6 __all__ = ["main"]
   7
   8
   9 def main_parser(parser=None):
  10     if parser is None:
  11         parser = argparse.ArgumentParser()
  12
  13     p_action = parser.add_subparsers(dest="action")
  14
  15     p_generate = p_action.add_parser("generate",
  16         help="generate RTLIL or Verilog from the design")
  17     p_generate.add_argument("-t", "--type", dest="generate_type",
  18         metavar="LANGUAGE", choices=["il", "v"],
  19         help="generate LANGUAGE (il for RTLIL, v for Verilog; default: %(default)s)")
  20     p_generate.add_argument("generate_file",
  21         metavar="FILE", type=argparse.FileType("w"), nargs="?",
  22         help="write generated code to FILE")
  23
  24     p_simulate = p_action.add_parser(
  25         "simulate", help="simulate the design")
  26     p_simulate.add_argument("-v", "--vcd-file",
  27         metavar="VCD-FILE", type=argparse.FileType("w"),
  28         help="write execution trace to VCD-FILE")
  29     p_simulate.add_argument("-w", "--gtkw-file",
  30         metavar="GTKW-FILE", type=argparse.FileType("w"),
  31         help="write GTKWave configuration to GTKW-FILE")
  32     p_simulate.add_argument("-p", "--period", dest="sync_period",
  33         metavar="TIME", type=float, default=1e-6,
  34         help="set 'sync' clock domain period to TIME (default: %(default)s)")
  35     p_simulate.add_argument("-c", "--clocks", dest="sync_clocks",
  36         metavar="COUNT", type=int, required=True,
  37         help="simulate for COUNT 'sync' clock periods")
  38
  39     return parser
  40
  41
  42 def main_runner(parser, args, design, platform=None, name="top", ports=()):
  43     if args.action == "generate":
  44         fragment = design.get_fragment(platform=platform)
  45         generate_type = args.generate_type
  46         if generate_type is None and args.generate_file:
  47             if args.generate_file.name.endswith(".v"):
  48                 generate_type = "v"
  49             if args.generate_file.name.endswith(".il"):
  50                 generate_type = "il"
  51         if generate_type is None:
  52             parser.error("specify file type explicitly with -t")
  53         if generate_type == "il":
  54             output = rtlil.convert(fragment, name=name, ports=ports)
  55         if generate_type == "v":
  56             output = verilog.convert(fragment, name=name, ports=ports)
  57         if args.generate_file:
  58             args.generate_file.write(output)
  59         else:
  60             print(output)
  61
  62     if args.action == "simulate":
  63         fragment = design.get_fragment(platform=platform)
  64         with pysim.Simulator(fragment,
  65                 vcd_file=args.vcd_file,
  66                 gtkw_file=args.gtkw_file,
  67                 traces=ports) as sim:
  68             sim.add_clock(args.sync_period)
  69             sim.run_until(args.sync_period * args.sync_clocks, run_passive=True)
  70
  71
  72 def main(*args, **kwargs):
  73     parser = main_parser()
  74     main_runner(parser, parser.parse_args(), *args, **kwargs)