nmigen/cli.py

   1 import argparse
   2
   3 from .back import rtlil, verilog, pysim
   4
   5
   6 __all__ = ["main"]
   7
   8
   9 def main_parser(parser=None):
  10     if parser is None:
  11         parser = argparse.ArgumentParser()
  12
  13     p_action = parser.add_subparsers(dest="action")
  14
  15     p_generate = p_action.add_parser("generate",
  16         help="generate RTLIL or Verilog from the design")
  17     p_generate.add_argument("-t", "--type", dest="generate_type",
  18         metavar="LANGUAGE", choices=["il", "v"],
  19         default="v",
  20         help="generate LANGUAGE (il for RTLIL, v for Verilog; default: %(default)s)")
  21     p_generate.add_argument("generate_file",
  22         metavar="FILE", type=argparse.FileType("w"), nargs="?",
  23         help="write generated code to FILE")
  24
  25     p_simulate = p_action.add_parser(
  26         "simulate", help="simulate the design")
  27     p_simulate.add_argument("-v", "--vcd-file",
  28         metavar="VCD-FILE", type=argparse.FileType("w"),
  29         help="write execution trace to VCD-FILE")
  30     p_simulate.add_argument("-w", "--gtkw-file",
  31         metavar="GTKW-FILE", type=argparse.FileType("w"),
  32         help="write GTKWave configuration to GTKW-FILE")
  33     p_simulate.add_argument("-p", "--period", dest="sync_period",
  34         metavar="TIME", type=float, default=1e-6,
  35         help="set 'sync' clock domain period to TIME (default: %(default)s)")
  36     p_simulate.add_argument("-c", "--clocks", dest="sync_clocks",
  37         metavar="COUNT", type=int, required=True,
  38         help="simulate for COUNT 'sync' clock periods")
  39
  40     return parser
  41
  42
  43 def main_runner(parser, args, design, platform=None, name="top", ports=()):
  44     if args.action == "generate":
  45         fragment = design.get_fragment(platform=platform)
  46         generate_type = args.generate_type
  47         if generate_type is None and args.generate_file:
  48             if args.generate_file.name.endswith(".v"):
  49                 generate_type = "v"
  50             if args.generate_file.name.endswith(".il"):
  51                 generate_type = "il"
  52         if generate_type is None:
  53             parser.error("specify file type explicitly with -t")
  54         if generate_type == "il":
  55             output = rtlil.convert(fragment, name=name, ports=ports)
  56         if generate_type == "v":
  57             output = verilog.convert(fragment, name=name, ports=ports)
  58         if args.generate_file:
  59             args.generate_file.write(output)
  60         else:
  61             print(output)
  62
  63     if args.action == "simulate":
  64         fragment = design.get_fragment(platform=platform)
  65         with pysim.Simulator(fragment,
  66                 vcd_file=args.vcd_file,
  67                 gtkw_file=args.gtkw_file,
  68                 traces=ports) as sim:
  69             sim.add_clock(args.sync_period)
  70             sim.run_until(args.sync_period * args.sync_clocks, run_passive=True)
  71
  72
  73 def main(*args, **kwargs):
  74     parser = main_parser()
  75     main_runner(parser, parser.parse_args(), *args, **kwargs)