3 from .hdl
.ir
import Fragment
4 from .back
import rtlil
, cxxrtl
, verilog
, pysim
10 def main_parser(parser
=None):
12 parser
= argparse
.ArgumentParser()
14 p_action
= parser
.add_subparsers(dest
="action")
16 p_generate
= p_action
.add_parser("generate",
17 help="generate RTLIL or Verilog from the design")
18 p_generate
.add_argument("-t", "--type", dest
="generate_type",
19 metavar
="LANGUAGE", choices
=["il", "cc", "v"],
21 help="generate LANGUAGE (il for RTLIL, v for Verilog; default: %(default)s)")
22 p_generate
.add_argument("generate_file",
23 metavar
="FILE", type=argparse
.FileType("w"), nargs
="?",
24 help="write generated code to FILE")
26 p_simulate
= p_action
.add_parser(
27 "simulate", help="simulate the design")
28 p_simulate
.add_argument("-v", "--vcd-file",
29 metavar
="VCD-FILE", type=argparse
.FileType("w"),
30 help="write execution trace to VCD-FILE")
31 p_simulate
.add_argument("-w", "--gtkw-file",
32 metavar
="GTKW-FILE", type=argparse
.FileType("w"),
33 help="write GTKWave configuration to GTKW-FILE")
34 p_simulate
.add_argument("-p", "--period", dest
="sync_period",
35 metavar
="TIME", type=float, default
=1e-6,
36 help="set 'sync' clock domain period to TIME (default: %(default)s)")
37 p_simulate
.add_argument("-c", "--clocks", dest
="sync_clocks",
38 metavar
="COUNT", type=int, required
=True,
39 help="simulate for COUNT 'sync' clock periods")
44 def main_runner(parser
, args
, design
, platform
=None, name
="top", ports
=()):
45 if args
.action
== "generate":
46 fragment
= Fragment
.get(design
, platform
)
47 generate_type
= args
.generate_type
48 if generate_type
is None and args
.generate_file
:
49 if args
.generate_file
.name
.endswith(".il"):
51 if args
.generate_file
.name
.endswith(".cc"):
53 if args
.generate_file
.name
.endswith(".v"):
55 if generate_type
is None:
56 parser
.error("specify file type explicitly with -t")
57 if generate_type
== "il":
58 output
= rtlil
.convert(fragment
, name
=name
, ports
=ports
)
59 if generate_type
== "cc":
60 output
= cxxrtl
.convert(fragment
, name
=name
, ports
=ports
)
61 if generate_type
== "v":
62 output
= verilog
.convert(fragment
, name
=name
, ports
=ports
)
63 if args
.generate_file
:
64 args
.generate_file
.write(output
)
68 if args
.action
== "simulate":
69 fragment
= Fragment
.get(design
, platform
)
70 sim
= pysim
.Simulator(fragment
)
71 sim
.add_clock(args
.sync_period
)
72 with sim
.write_vcd(vcd_file
=args
.vcd_file
, gtkw_file
=args
.gtkw_file
, traces
=ports
):
73 sim
.run_until(args
.sync_period
* args
.sync_clocks
, run_passive
=True)
76 def main(*args
, **kwargs
):
77 parser
= main_parser()
78 main_runner(parser
, parser
.parse_args(), *args
, **kwargs
)