nmigen/cli.py

   1 import argparse
   2
   3 from .hdl.ir import Fragment
   4 from .back import rtlil, verilog, pysim
   5
   6
   7 __all__ = ["main"]
   8
   9
  10 def main_parser(parser=None):
  11     if parser is None:
  12         parser = argparse.ArgumentParser()
  13
  14     p_action = parser.add_subparsers(dest="action")
  15
  16     p_generate = p_action.add_parser("generate",
  17         help="generate RTLIL or Verilog from the design")
  18     p_generate.add_argument("-t", "--type", dest="generate_type",
  19         metavar="LANGUAGE", choices=["il", "v"],
  20         default="v",
  21         help="generate LANGUAGE (il for RTLIL, v for Verilog; default: %(default)s)")
  22     p_generate.add_argument("generate_file",
  23         metavar="FILE", type=argparse.FileType("w"), nargs="?",
  24         help="write generated code to FILE")
  25
  26     p_simulate = p_action.add_parser(
  27         "simulate", help="simulate the design")
  28     p_simulate.add_argument("-v", "--vcd-file",
  29         metavar="VCD-FILE", type=argparse.FileType("w"),
  30         help="write execution trace to VCD-FILE")
  31     p_simulate.add_argument("-w", "--gtkw-file",
  32         metavar="GTKW-FILE", type=argparse.FileType("w"),
  33         help="write GTKWave configuration to GTKW-FILE")
  34     p_simulate.add_argument("-p", "--period", dest="sync_period",
  35         metavar="TIME", type=float, default=1e-6,
  36         help="set 'sync' clock domain period to TIME (default: %(default)s)")
  37     p_simulate.add_argument("-c", "--clocks", dest="sync_clocks",
  38         metavar="COUNT", type=int, required=True,
  39         help="simulate for COUNT 'sync' clock periods")
  40
  41     return parser
  42
  43
  44 def main_runner(parser, args, design, platform=None, name="top", ports=()):
  45     if args.action == "generate":
  46         fragment = Fragment.get(design, platform)
  47         generate_type = args.generate_type
  48         if generate_type is None and args.generate_file:
  49             if args.generate_file.name.endswith(".v"):
  50                 generate_type = "v"
  51             if args.generate_file.name.endswith(".il"):
  52                 generate_type = "il"
  53         if generate_type is None:
  54             parser.error("specify file type explicitly with -t")
  55         if generate_type == "il":
  56             output = rtlil.convert(fragment, name=name, ports=ports)
  57         if generate_type == "v":
  58             output = verilog.convert(fragment, name=name, ports=ports)
  59         if args.generate_file:
  60             args.generate_file.write(output)
  61         else:
  62             print(output)
  63
  64     if args.action == "simulate":
  65         fragment = Fragment.get(design, platform)
  66         sim = pysim.Simulator(fragment)
  67         sim.add_clock(args.sync_period)
  68         with sim.write_vcd(vcd_file=args.vcd_file, gtkw_file=args.gtkw_file, traces=ports):
  69             sim.run_until(args.sync_period * args.sync_clocks, run_passive=True)
  70
  71
  72 def main(*args, **kwargs):
  73     parser = main_parser()
  74     main_runner(parser, parser.parse_args(), *args, **kwargs)