nmigen/test/test_build_dsl.py

   1 from collections import OrderedDict
   2
   3 from ..build.dsl import *
   4 from .tools import *
   5
   6
   7 class PinsTestCase(FHDLTestCase):
   8     def test_basic(self):
   9         p = Pins("A0 A1 A2")
  10         self.assertEqual(repr(p), "(pins io A0 A1 A2)")
  11         self.assertEqual(len(p.names), 3)
  12         self.assertEqual(p.dir, "io")
  13         self.assertEqual(p.invert, False)
  14         self.assertEqual(list(p), ["A0", "A1", "A2"])
  15
  16     def test_invert(self):
  17         p = PinsN("A0")
  18         self.assertEqual(repr(p), "(pins-n io A0)")
  19         self.assertEqual(p.invert, True)
  20
  21     def test_conn(self):
  22         p = Pins("0 1 2", conn=("pmod", 0))
  23         self.assertEqual(list(p), ["pmod_0:0", "pmod_0:1", "pmod_0:2"])
  24
  25     def test_map_names(self):
  26         p = Pins("0 1 2", conn=("pmod", 0))
  27         mapping = {
  28             "pmod_0:0": "A0",
  29             "pmod_0:1": "A1",
  30             "pmod_0:2": "A2",
  31         }
  32         self.assertEqual(p.map_names(mapping, p), ["A0", "A1", "A2"])
  33
  34     def test_map_names_recur(self):
  35         p = Pins("0", conn=("pmod", 0))
  36         mapping = {
  37             "pmod_0:0": "ext_0:1",
  38             "ext_0:1":  "A1",
  39         }
  40         self.assertEqual(p.map_names(mapping, p), ["A1"])
  41
  42     def test_wrong_names(self):
  43         with self.assertRaises(TypeError,
  44                 msg="Names must be a whitespace-separated string, not ['A0', 'A1', 'A2']"):
  45             p = Pins(["A0", "A1", "A2"])
  46
  47     def test_wrong_dir(self):
  48         with self.assertRaises(TypeError,
  49                 msg="Direction must be one of \"i\", \"o\", \"oe\", or \"io\", not 'wrong'"):
  50             p = Pins("A0 A1", dir="wrong")
  51
  52     def test_wrong_map_names(self):
  53         p = Pins("0 1 2", conn=("pmod", 0))
  54         mapping = {
  55             "pmod_0:0": "A0",
  56         }
  57         with self.assertRaises(NameError,
  58                 msg="Resource (pins io pmod_0:0 pmod_0:1 pmod_0:2) refers to nonexistent "
  59                     "connector pin pmod_0:1"):
  60             p.map_names(mapping, p)
  61
  62     def test_wrong_assert_width(self):
  63         with self.assertRaises(AssertionError,
  64                 msg="3 names are specified (0 1 2), but 4 names are expected"):
  65             Pins("0 1 2", assert_width=4)
  66
  67
  68 class DiffPairsTestCase(FHDLTestCase):
  69     def test_basic(self):
  70         dp = DiffPairs(p="A0 A1", n="B0 B1")
  71         self.assertEqual(repr(dp), "(diffpairs io (p A0 A1) (n B0 B1))")
  72         self.assertEqual(dp.p.names, ["A0", "A1"])
  73         self.assertEqual(dp.n.names, ["B0", "B1"])
  74         self.assertEqual(dp.dir, "io")
  75         self.assertEqual(list(dp), [("A0", "B0"), ("A1", "B1")])
  76
  77     def test_invert(self):
  78         dp = DiffPairsN(p="A0", n="B0")
  79         self.assertEqual(repr(dp), "(diffpairs-n io (p A0) (n B0))")
  80         self.assertEqual(dp.p.names, ["A0"])
  81         self.assertEqual(dp.n.names, ["B0"])
  82         self.assertEqual(dp.invert, True)
  83
  84     def test_conn(self):
  85         dp = DiffPairs(p="0 1 2", n="3 4 5", conn=("pmod", 0))
  86         self.assertEqual(list(dp), [
  87             ("pmod_0:0", "pmod_0:3"),
  88             ("pmod_0:1", "pmod_0:4"),
  89             ("pmod_0:2", "pmod_0:5"),
  90         ])
  91
  92     def test_dir(self):
  93         dp = DiffPairs("A0", "B0", dir="o")
  94         self.assertEqual(dp.dir, "o")
  95         self.assertEqual(dp.p.dir, "o")
  96         self.assertEqual(dp.n.dir, "o")
  97
  98     def test_wrong_width(self):
  99         with self.assertRaises(TypeError,
 100                 msg="Positive and negative pins must have the same width, but (pins io A0) "
 101                     "and (pins io B0 B1) do not"):
 102             dp = DiffPairs("A0", "B0 B1")
 103
 104     def test_wrong_assert_width(self):
 105         with self.assertRaises(AssertionError,
 106                 msg="3 names are specified (0 1 2), but 4 names are expected"):
 107             DiffPairs("0 1 2", "3 4 5", assert_width=4)
 108
 109
 110 class AttrsTestCase(FHDLTestCase):
 111     def test_basic(self):
 112         a = Attrs(IO_STANDARD="LVCMOS33", PULLUP=1)
 113         self.assertEqual(a["IO_STANDARD"], "LVCMOS33")
 114         self.assertEqual(repr(a), "(attrs IO_STANDARD='LVCMOS33' PULLUP=1)")
 115
 116     def test_remove(self):
 117         a = Attrs(FOO=None)
 118         self.assertEqual(a["FOO"], None)
 119         self.assertEqual(repr(a), "(attrs !FOO)")
 120
 121     def test_callable(self):
 122         fn = lambda self: "FOO"
 123         a = Attrs(FOO=fn)
 124         self.assertEqual(a["FOO"], fn)
 125         self.assertEqual(repr(a), "(attrs FOO={!r})".format(fn))
 126
 127     def test_wrong_value(self):
 128         with self.assertRaises(TypeError,
 129                 msg="Value of attribute FOO must be None, int, str, or callable, not 1.0"):
 130             a = Attrs(FOO=1.0)
 131
 132
 133 class ClockTestCase(FHDLTestCase):
 134     def test_basic(self):
 135         c = Clock(1_000_000)
 136         self.assertEqual(c.frequency, 1e6)
 137         self.assertEqual(c.period, 1e-6)
 138         self.assertEqual(repr(c), "(clock 1000000.0)")
 139
 140
 141 class SubsignalTestCase(FHDLTestCase):
 142     def test_basic_pins(self):
 143         s = Subsignal("a", Pins("A0"), Attrs(IOSTANDARD="LVCMOS33"))
 144         self.assertEqual(repr(s),
 145             "(subsignal a (pins io A0) (attrs IOSTANDARD='LVCMOS33'))")
 146
 147     def test_basic_diffpairs(self):
 148         s = Subsignal("a", DiffPairs("A0", "B0"))
 149         self.assertEqual(repr(s),
 150             "(subsignal a (diffpairs io (p A0) (n B0)))")
 151
 152     def test_basic_subsignals(self):
 153         s = Subsignal("a",
 154                 Subsignal("b", Pins("A0")),
 155                 Subsignal("c", Pins("A1")))
 156         self.assertEqual(repr(s),
 157             "(subsignal a (subsignal b (pins io A0)) "
 158                          "(subsignal c (pins io A1)))")
 159
 160     def test_attrs(self):
 161         s = Subsignal("a",
 162                 Subsignal("b", Pins("A0")),
 163                 Subsignal("c", Pins("A0"), Attrs(SLEW="FAST")),
 164                 Attrs(IOSTANDARD="LVCMOS33"))
 165         self.assertEqual(s.attrs, {"IOSTANDARD": "LVCMOS33"})
 166         self.assertEqual(s.ios[0].attrs, {})
 167         self.assertEqual(s.ios[1].attrs, {"SLEW": "FAST"})
 168
 169     def test_attrs_many(self):
 170         s = Subsignal("a", Pins("A0"), Attrs(SLEW="FAST"), Attrs(PULLUP="1"))
 171         self.assertEqual(s.attrs, {"SLEW": "FAST", "PULLUP": "1"})
 172
 173     def test_clock(self):
 174         s = Subsignal("a", Pins("A0"), Clock(1e6))
 175         self.assertEqual(s.clock.frequency, 1e6)
 176
 177     def test_wrong_empty_io(self):
 178         with self.assertRaises(ValueError, msg="Missing I/O constraints"):
 179             s = Subsignal("a")
 180
 181     def test_wrong_io(self):
 182         with self.assertRaises(TypeError,
 183                 msg="Constraint must be one of Pins, DiffPairs, Subsignal, Attrs, or Clock, "
 184                     "not 'wrong'"):
 185             s = Subsignal("a", "wrong")
 186
 187     def test_wrong_pins(self):
 188         with self.assertRaises(TypeError,
 189                 msg="Pins and DiffPairs are incompatible with other location or subsignal "
 190                     "constraints, but (pins io A1) appears after (pins io A0)"):
 191             s = Subsignal("a", Pins("A0"), Pins("A1"))
 192
 193     def test_wrong_diffpairs(self):
 194         with self.assertRaises(TypeError,
 195                 msg="Pins and DiffPairs are incompatible with other location or subsignal "
 196                     "constraints, but (pins io A1) appears after (diffpairs io (p A0) (n B0))"):
 197             s = Subsignal("a", DiffPairs("A0", "B0"), Pins("A1"))
 198
 199     def test_wrong_subsignals(self):
 200         with self.assertRaises(TypeError,
 201                 msg="Pins and DiffPairs are incompatible with other location or subsignal "
 202                     "constraints, but (pins io B0) appears after (subsignal b (pins io A0))"):
 203             s = Subsignal("a", Subsignal("b", Pins("A0")), Pins("B0"))
 204
 205     def test_wrong_clock(self):
 206         with self.assertRaises(TypeError,
 207                 msg="Clock constraint can only be applied to Pins or DiffPairs, not "
 208                     "(subsignal b (pins io A0))"):
 209             s = Subsignal("a", Subsignal("b", Pins("A0")), Clock(1e6))
 210
 211     def test_wrong_clock_many(self):
 212         with self.assertRaises(ValueError,
 213                 msg="Clock constraint can be applied only once"):
 214             s = Subsignal("a", Pins("A0"), Clock(1e6), Clock(1e7))
 215
 216
 217 class ResourceTestCase(FHDLTestCase):
 218     def test_basic(self):
 219         r = Resource("serial", 0,
 220                 Subsignal("tx", Pins("A0", dir="o")),
 221                 Subsignal("rx", Pins("A1", dir="i")),
 222                 Attrs(IOSTANDARD="LVCMOS33"))
 223         self.assertEqual(repr(r), "(resource serial 0"
 224                                   " (subsignal tx (pins o A0))"
 225                                   " (subsignal rx (pins i A1))"
 226                                   " (attrs IOSTANDARD='LVCMOS33'))")
 227
 228     def test_family(self):
 229         ios = [Subsignal("clk", Pins("A0", dir="o"))]
 230         r1  = Resource.family(0, default_name="spi", ios=ios)
 231         r2  = Resource.family("spi_flash", 0, default_name="spi", ios=ios)
 232         r3  = Resource.family("spi_flash", 0, default_name="spi", ios=ios, name_suffix="4x")
 233         r4  = Resource.family(0, default_name="spi", ios=ios, name_suffix="2x")
 234         self.assertEqual(r1.name, "spi")
 235         self.assertEqual(r1.ios, ios)
 236         self.assertEqual(r2.name, "spi_flash")
 237         self.assertEqual(r2.ios, ios)
 238         self.assertEqual(r3.name, "spi_flash_4x")
 239         self.assertEqual(r3.ios, ios)
 240         self.assertEqual(r4.name, "spi_2x")
 241         self.assertEqual(r4.ios, ios)
 242
 243
 244 class ConnectorTestCase(FHDLTestCase):
 245     def test_string(self):
 246         c = Connector("pmod", 0, "A0 A1 A2 A3 - - A4 A5 A6 A7 - -")
 247         self.assertEqual(c.name, "pmod")
 248         self.assertEqual(c.number, 0)
 249         self.assertEqual(c.mapping, OrderedDict([
 250             ("1", "A0"),
 251             ("2", "A1"),
 252             ("3", "A2"),
 253             ("4", "A3"),
 254             ("7", "A4"),
 255             ("8", "A5"),
 256             ("9", "A6"),
 257             ("10", "A7"),
 258         ]))
 259         self.assertEqual(list(c), [
 260             ("pmod_0:1", "A0"),
 261             ("pmod_0:2", "A1"),
 262             ("pmod_0:3", "A2"),
 263             ("pmod_0:4", "A3"),
 264             ("pmod_0:7", "A4"),
 265             ("pmod_0:8", "A5"),
 266             ("pmod_0:9", "A6"),
 267             ("pmod_0:10", "A7"),
 268         ])
 269         self.assertEqual(repr(c),
 270             "(connector pmod 0 1=>A0 2=>A1 3=>A2 4=>A3 7=>A4 8=>A5 9=>A6 10=>A7)")
 271
 272     def test_dict(self):
 273         c = Connector("ext", 1, {"DP0": "A0", "DP1": "A1"})
 274         self.assertEqual(c.name, "ext")
 275         self.assertEqual(c.number, 1)
 276         self.assertEqual(c.mapping, OrderedDict([
 277             ("DP0", "A0"),
 278             ("DP1", "A1"),
 279         ]))
 280
 281     def test_conn(self):
 282         c = Connector("pmod", 0, "0 1 2 3 - - 4 5 6 7 - -", conn=("expansion", 0))
 283         self.assertEqual(c.mapping, OrderedDict([
 284             ("1", "expansion_0:0"),
 285             ("2", "expansion_0:1"),
 286             ("3", "expansion_0:2"),
 287             ("4", "expansion_0:3"),
 288             ("7", "expansion_0:4"),
 289             ("8", "expansion_0:5"),
 290             ("9", "expansion_0:6"),
 291             ("10", "expansion_0:7"),
 292         ]))
 293
 294     def test_wrong_io(self):
 295         with self.assertRaises(TypeError,
 296                 msg="Connector I/Os must be a dictionary or a string, not []"):
 297             Connector("pmod", 0, [])
 298
 299     def test_wrong_dict_key_value(self):
 300         with self.assertRaises(TypeError,
 301                 msg="Connector pin name must be a string, not 0"):
 302             Connector("pmod", 0, {0: "A"})
 303         with self.assertRaises(TypeError,
 304                 msg="Platform pin name must be a string, not 0"):
 305             Connector("pmod", 0, {"A": 0})