nmigen/test/test_build_dsl.py

   1 from ..build.dsl import *
   2 from .tools import *
   3
   4
   5 class PinsTestCase(FHDLTestCase):
   6     def test_basic(self):
   7         p = Pins("A0 A1 A2")
   8         self.assertEqual(repr(p), "(pins io A0 A1 A2)")
   9         self.assertEqual(len(p.names), 3)
  10         self.assertEqual(p.dir, "io")
  11         self.assertEqual(list(p), ["A0", "A1", "A2"])
  12
  13     def test_wrong_names(self):
  14         with self.assertRaises(TypeError,
  15                 msg="Names must be a whitespace-separated string, not ['A0', 'A1', 'A2']"):
  16             p = Pins(["A0", "A1", "A2"])
  17
  18     def test_wrong_dir(self):
  19         with self.assertRaises(TypeError,
  20                 msg="Direction must be one of \"i\", \"o\" or \"io\", not 'wrong'"):
  21             p = Pins("A0 A1", dir="wrong")
  22
  23
  24 class DiffPairsTestCase(FHDLTestCase):
  25     def test_basic(self):
  26         dp = DiffPairs(p="A0 A1", n="B0 B1")
  27         self.assertEqual(repr(dp), "(diffpairs io (p A0 A1) (n B0 B1))")
  28         self.assertEqual(dp.p.names, ["A0", "A1"])
  29         self.assertEqual(dp.n.names, ["B0", "B1"])
  30         self.assertEqual(dp.dir, "io")
  31         self.assertEqual(list(dp), [("A0", "B0"), ("A1", "B1")])
  32
  33     def test_dir(self):
  34         dp = DiffPairs("A0", "B0", dir="o")
  35         self.assertEqual(dp.dir, "o")
  36         self.assertEqual(dp.p.dir, "o")
  37         self.assertEqual(dp.n.dir, "o")
  38
  39     def test_wrong_width(self):
  40         with self.assertRaises(TypeError,
  41                 msg="Positive and negative pins must have the same width, but (pins io A0) "
  42                     "and (pins io B0 B1) do not"):
  43             dp = DiffPairs("A0", "B0 B1")
  44
  45
  46 class SubsignalTestCase(FHDLTestCase):
  47     def test_basic_pins(self):
  48         s = Subsignal("a", Pins("A0"), extras={"IOSTANDARD": "LVCMOS33"})
  49         self.assertEqual(repr(s), "(subsignal a (pins io A0) IOSTANDARD=LVCMOS33)")
  50
  51     def test_basic_diffpairs(self):
  52         s = Subsignal("a", DiffPairs("A0", "B0"))
  53         self.assertEqual(repr(s), "(subsignal a (diffpairs io (p A0) (n B0)) )")
  54
  55     def test_basic_subsignals(self):
  56         s = Subsignal("a",
  57                 Subsignal("b", Pins("A0")),
  58                 Subsignal("c", Pins("A1")))
  59         self.assertEqual(repr(s),
  60                 "(subsignal a (subsignal b (pins io A0) ) (subsignal c (pins io A1) ) )")
  61
  62     def test_extras(self):
  63         s = Subsignal("a",
  64                 Subsignal("b", Pins("A0")),
  65                 Subsignal("c", Pins("A0"), extras={"SLEW": "FAST"}),
  66                 extras={"IOSTANDARD": "LVCMOS33"})
  67         self.assertEqual(s.extras, {"IOSTANDARD": "LVCMOS33"})
  68         self.assertEqual(s.io[0].extras, {"IOSTANDARD": "LVCMOS33"})
  69         self.assertEqual(s.io[1].extras, {"SLEW": "FAST", "IOSTANDARD": "LVCMOS33"})
  70
  71     def test_empty_io(self):
  72         with self.assertRaises(TypeError, msg="Missing I/O constraints"):
  73             s = Subsignal("a")
  74
  75     def test_wrong_io(self):
  76         with self.assertRaises(TypeError,
  77                 msg="I/O constraint must be one of Pins, DiffPairs or Subsignal, not 'wrong'"):
  78             s = Subsignal("a", "wrong")
  79
  80     def test_wrong_pins(self):
  81         with self.assertRaises(TypeError,
  82                 msg="Pins and DiffPairs cannot be followed by more I/O constraints, but "
  83                     "(pins io A0) is followed by (pins io A1)"):
  84             s = Subsignal("a", Pins("A0"), Pins("A1"))
  85
  86     def test_wrong_diffpairs(self):
  87         with self.assertRaises(TypeError,
  88                 msg="Pins and DiffPairs cannot be followed by more I/O constraints, but "
  89                     "(diffpairs io (p A0) (n B0)) is followed by "
  90                     "(pins io A1)"):
  91             s = Subsignal("a", DiffPairs("A0", "B0"), Pins("A1"))
  92
  93     def test_wrong_subsignals(self):
  94         with self.assertRaises(TypeError,
  95                 msg="A Subsignal can only be followed by more Subsignals, but "
  96                     "(subsignal b (pins io A0) ) is followed by (pins io B0)"):
  97             s = Subsignal("a", Subsignal("b", Pins("A0")), Pins("B0"))
  98
  99     def test_wrong_extras(self):
 100         with self.assertRaises(TypeError,
 101                 msg="Extra constraints must be a dict, not [(pins io B0)]"):
 102             s = Subsignal("a", Pins("A0"), extras=[Pins("B0")])
 103         with self.assertRaises(TypeError,
 104                 msg="Extra constraint key must be a string, not 1"):
 105             s = Subsignal("a", Pins("A0"), extras={1: 2})
 106         with self.assertRaises(TypeError,
 107                 msg="Extra constraint value must be a string, not 2"):
 108             s = Subsignal("a", Pins("A0"), extras={"1": 2})
 109
 110
 111 class ResourceTestCase(FHDLTestCase):
 112     def test_basic(self):
 113         r = Resource("serial", 0,
 114                 Subsignal("tx", Pins("A0", dir="o")),
 115                 Subsignal("rx", Pins("A1", dir="i")),
 116                 extras={"IOSTANDARD": "LVCMOS33"})
 117         self.assertEqual(repr(r), "(resource serial 0"
 118                                   " (subsignal tx (pins o A0) IOSTANDARD=LVCMOS33)"
 119                                   " (subsignal rx (pins i A1) IOSTANDARD=LVCMOS33)"
 120                                   " IOSTANDARD=LVCMOS33)")