nmigen/test/test_build_dsl.py

   1 from ..build.dsl import *
   2 from .tools import *
   3
   4
   5 class PinsTestCase(FHDLTestCase):
   6     def test_basic(self):
   7         p = Pins("A0 A1 A2")
   8         self.assertEqual(repr(p), "(pins A0 A1 A2 io)")
   9         self.assertEqual(len(p.names), 3)
  10         self.assertEqual(p.dir, "io")
  11
  12     def test_wrong_names(self):
  13         with self.assertRaises(TypeError,
  14                 msg="Names must be a whitespace-separated string, not ['A0', 'A1', 'A2']"):
  15             p = Pins(["A0", "A1", "A2"])
  16
  17     def test_wrong_dir(self):
  18         with self.assertRaises(TypeError,
  19                 msg="Direction must be one of \"i\", \"o\" or \"io\", not 'wrong'"):
  20             p = Pins("A0 A1", dir="wrong")
  21
  22
  23 class DiffPairsTestCase(FHDLTestCase):
  24     def test_basic(self):
  25         dp = DiffPairs(p="A0 A1", n="B0 B1")
  26         self.assertEqual(repr(dp), "(diffpairs (pins A0 A1 io) (pins B0 B1 io))")
  27         self.assertEqual(dp.p.names, ["A0", "A1"])
  28         self.assertEqual(dp.n.names, ["B0", "B1"])
  29         self.assertEqual(dp.dir, "io")
  30
  31     def test_dir(self):
  32         dp = DiffPairs("A0", "B0", dir="o")
  33         self.assertEqual(dp.dir, "o")
  34         self.assertEqual(dp.p.dir, "o")
  35         self.assertEqual(dp.n.dir, "o")
  36
  37     def test_wrong_width(self):
  38         with self.assertRaises(TypeError,
  39                 msg="Positive and negative pins must have the same width, but (pins A0 io) and "
  40                     "(pins B0 B1 io) do not"):
  41             dp = DiffPairs("A0", "B0 B1")
  42
  43
  44 class SubsignalTestCase(FHDLTestCase):
  45     def test_basic_pins(self):
  46         s = Subsignal("a", Pins("A0"), extras=["IOSTANDARD=LVCMOS33"])
  47         self.assertEqual(repr(s), "(subsignal a (pins A0 io) IOSTANDARD=LVCMOS33)")
  48
  49     def test_basic_diffpairs(self):
  50         s = Subsignal("a", DiffPairs("A0", "B0"))
  51         self.assertEqual(repr(s), "(subsignal a (diffpairs (pins A0 io) (pins B0 io)) )")
  52
  53     def test_basic_subsignals(self):
  54         s = Subsignal("a",
  55                 Subsignal("b", Pins("A0")),
  56                 Subsignal("c", Pins("A1")))
  57         self.assertEqual(repr(s),
  58                 "(subsignal a (subsignal b (pins A0 io) ) (subsignal c (pins A1 io) ) )")
  59
  60     def test_extras(self):
  61         s = Subsignal("a",
  62                 Subsignal("b", Pins("A0")),
  63                 Subsignal("c", Pins("A0"), extras=["SLEW=FAST"]),
  64                 extras=["IOSTANDARD=LVCMOS33"])
  65         self.assertEqual(s.extras, ["IOSTANDARD=LVCMOS33"])
  66         self.assertEqual(s.io[0].extras, ["IOSTANDARD=LVCMOS33"])
  67         self.assertEqual(s.io[1].extras, ["SLEW=FAST", "IOSTANDARD=LVCMOS33"])
  68
  69     def test_empty_io(self):
  70         with self.assertRaises(TypeError, msg="Missing I/O constraints"):
  71             s = Subsignal("a")
  72
  73     def test_wrong_io(self):
  74         with self.assertRaises(TypeError,
  75                 msg="I/O constraint must be one of Pins, DiffPairs or Subsignal, not 'wrong'"):
  76             s = Subsignal("a", "wrong")
  77
  78     def test_wrong_pins(self):
  79         with self.assertRaises(TypeError,
  80                 msg="Pins and DiffPairs cannot be followed by more I/O constraints, but "
  81                     "(pins A0 io) is followed by (pins A1 io)"):
  82             s = Subsignal("a", Pins("A0"), Pins("A1"))
  83
  84     def test_wrong_diffpairs(self):
  85         with self.assertRaises(TypeError,
  86                 msg="Pins and DiffPairs cannot be followed by more I/O constraints, but "
  87                     "(diffpairs (pins A0 io) (pins B0 io)) is followed by (pins A1 io)"):
  88             s = Subsignal("a", DiffPairs("A0", "B0"), Pins("A1"))
  89
  90     def test_wrong_subsignals(self):
  91         with self.assertRaises(TypeError,
  92                 msg="A Subsignal can only be followed by more Subsignals, but "
  93                     "(subsignal b (pins A0 io) ) is followed by (pins B0 io)"):
  94             s = Subsignal("a", Subsignal("b", Pins("A0")), Pins("B0"))
  95
  96     def test_wrong_extras(self):
  97         with self.assertRaises(TypeError,
  98                 msg="Extra constraint must be a string, not (pins B0 io)"):
  99             s = Subsignal("a", Pins("A0"), extras=[Pins("B0")])
 100
 101
 102 class ResourceTestCase(FHDLTestCase):
 103     def test_basic(self):
 104         r = Resource("serial", 0,
 105                 Subsignal("tx", Pins("A0", dir="o")),
 106                 Subsignal("rx", Pins("A1", dir="i")),
 107                 extras=["IOSTANDARD=LVCMOS33"])
 108         self.assertEqual(repr(r), "(resource serial 0"
 109                                   " (subsignal tx (pins A0 o) IOSTANDARD=LVCMOS33)"
 110                                   " (subsignal rx (pins A1 i) IOSTANDARD=LVCMOS33)"
 111                                   " IOSTANDARD=LVCMOS33)")