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hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.
[nmigen.git]
/
nmigen
/
test
/
test_compat.py
1
from
..
hdl
.
ir
import
Fragment
2
from
..
compat
import
*
3
from
.
tools
import
*
4
5
6
class
CompatTestCase
(
FHDLTestCase
):
7
def
test_fragment_get
(
self
):
8
m
=
Module
()
9
f
=
Fragment
.
get
(
m
,
platform
=
None
)