hdl.xfrm: implement SwitchCleaner, for pruning empty switches.
[nmigen.git] / nmigen / test / test_hdl_cd.py
1 from ..hdl.cd import *
2 from .tools import *
3
4
5 class ClockDomainTestCase(FHDLTestCase):
6 def test_name(self):
7 sync = ClockDomain()
8 self.assertEqual(sync.name, "sync")
9 self.assertEqual(sync.clk.name, "clk")
10 self.assertEqual(sync.rst.name, "rst")
11 pix = ClockDomain()
12 self.assertEqual(pix.name, "pix")
13 self.assertEqual(pix.clk.name, "pix_clk")
14 self.assertEqual(pix.rst.name, "pix_rst")
15 cd_pix = ClockDomain()
16 self.assertEqual(pix.name, "pix")
17 dom = [ClockDomain("foo")][0]
18 self.assertEqual(dom.name, "foo")
19 with self.assertRaises(ValueError,
20 msg="Clock domain name must be specified explicitly"):
21 ClockDomain()
22
23 def test_with_reset(self):
24 pix = ClockDomain()
25 self.assertIsNotNone(pix.clk)
26 self.assertIsNotNone(pix.rst)
27 self.assertFalse(pix.async_reset)
28
29 def test_without_reset(self):
30 pix = ClockDomain(reset_less=True)
31 self.assertIsNotNone(pix.clk)
32 self.assertIsNone(pix.rst)
33 self.assertFalse(pix.async_reset)
34
35 def test_async_reset(self):
36 pix = ClockDomain(async_reset=True)
37 self.assertIsNotNone(pix.clk)
38 self.assertIsNotNone(pix.rst)
39 self.assertTrue(pix.async_reset)
40
41 def test_rename(self):
42 sync = ClockDomain()
43 self.assertEqual(sync.name, "sync")
44 self.assertEqual(sync.clk.name, "clk")
45 self.assertEqual(sync.rst.name, "rst")
46 sync.rename("pix")
47 self.assertEqual(sync.name, "pix")
48 self.assertEqual(sync.clk.name, "pix_clk")
49 self.assertEqual(sync.rst.name, "pix_rst")
50
51 def test_rename_reset_less(self):
52 sync = ClockDomain(reset_less=True)
53 self.assertEqual(sync.name, "sync")
54 self.assertEqual(sync.clk.name, "clk")
55 sync.rename("pix")
56 self.assertEqual(sync.name, "pix")
57 self.assertEqual(sync.clk.name, "pix_clk")