5 class ClockDomainTestCase(FHDLTestCase
):
8 self
.assertEqual(sync
.name
, "sync")
9 self
.assertEqual(sync
.clk
.name
, "clk")
10 self
.assertEqual(sync
.rst
.name
, "rst")
12 self
.assertEqual(pix
.name
, "pix")
13 self
.assertEqual(pix
.clk
.name
, "pix_clk")
14 self
.assertEqual(pix
.rst
.name
, "pix_rst")
15 cd_pix
= ClockDomain()
16 self
.assertEqual(pix
.name
, "pix")
17 dom
= [ClockDomain("foo")][0]
18 self
.assertEqual(dom
.name
, "foo")
19 with self
.assertRaises(ValueError,
20 msg
="Clock domain name must be specified explicitly"):
23 def test_with_reset(self
):
25 self
.assertIsNotNone(pix
.clk
)
26 self
.assertIsNotNone(pix
.rst
)
27 self
.assertFalse(pix
.async_reset
)
29 def test_without_reset(self
):
30 pix
= ClockDomain(reset_less
=True)
31 self
.assertIsNotNone(pix
.clk
)
32 self
.assertIsNone(pix
.rst
)
33 self
.assertFalse(pix
.async_reset
)
35 def test_async_reset(self
):
36 pix
= ClockDomain(async_reset
=True)
37 self
.assertIsNotNone(pix
.clk
)
38 self
.assertIsNotNone(pix
.rst
)
39 self
.assertTrue(pix
.async_reset
)
41 def test_rename(self
):
43 self
.assertEqual(sync
.name
, "sync")
44 self
.assertEqual(sync
.clk
.name
, "clk")
45 self
.assertEqual(sync
.rst
.name
, "rst")
47 self
.assertEqual(sync
.name
, "pix")
48 self
.assertEqual(sync
.clk
.name
, "pix_clk")
49 self
.assertEqual(sync
.rst
.name
, "pix_rst")
51 def test_rename_reset_less(self
):
52 sync
= ClockDomain(reset_less
=True)
53 self
.assertEqual(sync
.name
, "sync")
54 self
.assertEqual(sync
.clk
.name
, "clk")
56 self
.assertEqual(sync
.name
, "pix")
57 self
.assertEqual(sync
.clk
.name
, "pix_clk")