nmigen/test/test_hdl_mem.py

   1 from ..hdl.ast import *
   2 from ..hdl.mem import *
   3 from .tools import *
   4
   5
   6 class MemoryTestCase(FHDLTestCase):
   7     def test_name(self):
   8         m1 = Memory(width=8, depth=4)
   9         self.assertEqual(m1.name, "m1")
  10         m2 = [Memory(width=8, depth=4)][0]
  11         self.assertEqual(m2.name, "$memory")
  12         m3 = Memory(width=8, depth=4, name="foo")
  13         self.assertEqual(m3.name, "foo")
  14
  15     def test_geometry(self):
  16         m = Memory(width=8, depth=4)
  17         self.assertEqual(m.width, 8)
  18         self.assertEqual(m.depth, 4)
  19
  20     def test_geometry_wrong(self):
  21         with self.assertRaises(TypeError,
  22                 msg="Memory width must be a non-negative integer, not '-1'"):
  23             m = Memory(width=-1, depth=4)
  24         with self.assertRaises(TypeError,
  25                 msg="Memory depth must be a non-negative integer, not '-1'"):
  26             m = Memory(width=8, depth=-1)
  27
  28     def test_init(self):
  29         m = Memory(width=8, depth=4, init=range(4))
  30         self.assertEqual(m.init, [0, 1, 2, 3])
  31
  32     def test_init_wrong(self):
  33         with self.assertRaises(ValueError,
  34                 msg="Memory initialization value count exceed memory depth (8 > 4)"):
  35             m = Memory(width=8, depth=4, init=range(8))
  36
  37     def test_read_port_transparent(self):
  38         mem    = Memory(width=8, depth=4)
  39         rdport = mem.read_port()
  40         self.assertEqual(rdport.memory, mem)
  41         self.assertEqual(rdport.domain, "sync")
  42         self.assertEqual(rdport.synchronous, True)
  43         self.assertEqual(rdport.transparent, True)
  44         self.assertEqual(len(rdport.addr), 2)
  45         self.assertEqual(len(rdport.data), 8)
  46         self.assertEqual(len(rdport.en), 1)
  47         self.assertIsInstance(rdport.en, Const)
  48         self.assertEqual(rdport.en.value, 1)
  49
  50     def test_read_port_non_transparent(self):
  51         mem    = Memory(width=8, depth=4)
  52         rdport = mem.read_port(transparent=False)
  53         self.assertEqual(rdport.memory, mem)
  54         self.assertEqual(rdport.domain, "sync")
  55         self.assertEqual(rdport.synchronous, True)
  56         self.assertEqual(rdport.transparent, False)
  57         self.assertEqual(len(rdport.en), 1)
  58         self.assertIsInstance(rdport.en, Signal)
  59
  60     def test_read_port_asynchronous(self):
  61         mem    = Memory(width=8, depth=4)
  62         rdport = mem.read_port(synchronous=False)
  63         self.assertEqual(rdport.memory, mem)
  64         self.assertEqual(rdport.domain, "sync")
  65         self.assertEqual(rdport.synchronous, False)
  66         self.assertEqual(rdport.transparent, True)
  67         self.assertEqual(len(rdport.en), 1)
  68         self.assertIsInstance(rdport.en, Const)
  69         self.assertEqual(rdport.en.value, 1)
  70
  71     def test_read_port_wrong(self):
  72         mem = Memory(width=8, depth=4)
  73         with self.assertRaises(ValueError,
  74                 msg="Read port cannot be simultaneously asynchronous and non-transparent"):
  75             mem.read_port(synchronous=False, transparent=False)
  76
  77     def test_write_port(self):
  78         mem    = Memory(width=8, depth=4)
  79         wrport = mem.write_port()
  80         self.assertEqual(wrport.memory, mem)
  81         self.assertEqual(wrport.domain, "sync")
  82         self.assertEqual(wrport.priority, 0)
  83         self.assertEqual(wrport.granularity, 8)
  84         self.assertEqual(len(wrport.addr), 2)
  85         self.assertEqual(len(wrport.data), 8)
  86         self.assertEqual(len(wrport.en), 1)
  87
  88     def test_write_port_granularity(self):
  89         mem    = Memory(width=8, depth=4)
  90         wrport = mem.write_port(granularity=2)
  91         self.assertEqual(wrport.memory, mem)
  92         self.assertEqual(wrport.domain, "sync")
  93         self.assertEqual(wrport.priority, 0)
  94         self.assertEqual(wrport.granularity, 2)
  95         self.assertEqual(len(wrport.addr), 2)
  96         self.assertEqual(len(wrport.data), 8)
  97         self.assertEqual(len(wrport.en), 4)
  98
  99     def test_write_port_granularity_wrong(self):
 100         mem = Memory(width=8, depth=4)
 101         with self.assertRaises(TypeError,
 102                 msg="Write port granularity must be a non-negative integer, not '-1'"):
 103             mem.write_port(granularity=-1)
 104         with self.assertRaises(ValueError,
 105                 msg="Write port granularity must not be greater than memory width (10 > 8)"):
 106             mem.write_port(granularity=10)
 107         with self.assertRaises(ValueError,
 108                 msg="Write port granularity must divide memory width evenly"):
 109             mem.write_port(granularity=3)