nmigen/test/test_hdl_mem.py

   1 from ..hdl.ast import *
   2 from ..hdl.mem import *
   3 from .tools import *
   4
   5
   6 class MemoryTestCase(FHDLTestCase):
   7     def test_name(self):
   8         m1 = Memory(width=8, depth=4)
   9         self.assertEqual(m1.name, "m1")
  10         m2 = [Memory(width=8, depth=4)][0]
  11         self.assertEqual(m2.name, "$memory")
  12         m3 = Memory(width=8, depth=4, name="foo")
  13         self.assertEqual(m3.name, "foo")
  14
  15     def test_geometry(self):
  16         m = Memory(width=8, depth=4)
  17         self.assertEqual(m.width, 8)
  18         self.assertEqual(m.depth, 4)
  19
  20     def test_geometry_wrong(self):
  21         with self.assertRaises(TypeError,
  22                 msg="Memory width must be a non-negative integer, not '-1'"):
  23             m = Memory(width=-1, depth=4)
  24         with self.assertRaises(TypeError,
  25                 msg="Memory depth must be a non-negative integer, not '-1'"):
  26             m = Memory(width=8, depth=-1)
  27
  28     def test_init(self):
  29         m = Memory(width=8, depth=4, init=range(4))
  30         self.assertEqual(m.init, [0, 1, 2, 3])
  31
  32     def test_init_wrong_count(self):
  33         with self.assertRaises(ValueError,
  34                 msg="Memory initialization value count exceed memory depth (8 > 4)"):
  35             m = Memory(width=8, depth=4, init=range(8))
  36
  37     def test_init_wrong_type(self):
  38         with self.assertRaises(TypeError,
  39                 msg="Memory initialization value at address 1: "
  40                     "'str' object cannot be interpreted as an integer"):
  41             m = Memory(width=8, depth=4, init=[1, "0"])
  42
  43     def test_read_port_transparent(self):
  44         mem    = Memory(width=8, depth=4)
  45         rdport = mem.read_port()
  46         self.assertEqual(rdport.memory, mem)
  47         self.assertEqual(rdport.domain, "sync")
  48         self.assertEqual(rdport.transparent, True)
  49         self.assertEqual(len(rdport.addr), 2)
  50         self.assertEqual(len(rdport.data), 8)
  51         self.assertEqual(len(rdport.en), 1)
  52         self.assertIsInstance(rdport.en, Const)
  53         self.assertEqual(rdport.en.value, 1)
  54
  55     def test_read_port_non_transparent(self):
  56         mem    = Memory(width=8, depth=4)
  57         rdport = mem.read_port(transparent=False)
  58         self.assertEqual(rdport.memory, mem)
  59         self.assertEqual(rdport.domain, "sync")
  60         self.assertEqual(rdport.transparent, False)
  61         self.assertEqual(len(rdport.en), 1)
  62         self.assertIsInstance(rdport.en, Signal)
  63         self.assertEqual(rdport.en.reset, 1)
  64
  65     def test_read_port_asynchronous(self):
  66         mem    = Memory(width=8, depth=4)
  67         rdport = mem.read_port(domain="comb")
  68         self.assertEqual(rdport.memory, mem)
  69         self.assertEqual(rdport.domain, "comb")
  70         self.assertEqual(rdport.transparent, True)
  71         self.assertEqual(len(rdport.en), 1)
  72         self.assertIsInstance(rdport.en, Const)
  73         self.assertEqual(rdport.en.value, 1)
  74
  75     def test_read_port_wrong(self):
  76         mem = Memory(width=8, depth=4)
  77         with self.assertRaises(ValueError,
  78                 msg="Read port cannot be simultaneously asynchronous and non-transparent"):
  79             mem.read_port(domain="comb", transparent=False)
  80
  81     def test_write_port(self):
  82         mem    = Memory(width=8, depth=4)
  83         wrport = mem.write_port()
  84         self.assertEqual(wrport.memory, mem)
  85         self.assertEqual(wrport.domain, "sync")
  86         self.assertEqual(wrport.priority, 0)
  87         self.assertEqual(wrport.granularity, 8)
  88         self.assertEqual(len(wrport.addr), 2)
  89         self.assertEqual(len(wrport.data), 8)
  90         self.assertEqual(len(wrport.en), 1)
  91
  92     def test_write_port_granularity(self):
  93         mem    = Memory(width=8, depth=4)
  94         wrport = mem.write_port(granularity=2)
  95         self.assertEqual(wrport.memory, mem)
  96         self.assertEqual(wrport.domain, "sync")
  97         self.assertEqual(wrport.priority, 0)
  98         self.assertEqual(wrport.granularity, 2)
  99         self.assertEqual(len(wrport.addr), 2)
 100         self.assertEqual(len(wrport.data), 8)
 101         self.assertEqual(len(wrport.en), 4)
 102
 103     def test_write_port_granularity_wrong(self):
 104         mem = Memory(width=8, depth=4)
 105         with self.assertRaises(TypeError,
 106                 msg="Write port granularity must be a non-negative integer, not '-1'"):
 107             mem.write_port(granularity=-1)
 108         with self.assertRaises(ValueError,
 109                 msg="Write port granularity must not be greater than memory width (10 > 8)"):
 110             mem.write_port(granularity=10)
 111         with self.assertRaises(ValueError,
 112                 msg="Write port granularity must divide memory width evenly"):
 113             mem.write_port(granularity=3)
 114
 115
 116 class DummyPortTestCase(FHDLTestCase):
 117     def test_name(self):
 118         p1 = DummyPort(width=8, addr_bits=2)
 119         self.assertEqual(p1.addr.name, "p1_addr")
 120         p2 = [DummyPort(width=8, addr_bits=2)][0]
 121         self.assertEqual(p2.addr.name, "dummy_addr")
 122         p3 = DummyPort(width=8, addr_bits=2, name="foo")
 123         self.assertEqual(p3.addr.name, "foo_addr")
 124
 125     def test_sizes(self):
 126         p1 = DummyPort(width=8, addr_bits=2)
 127         self.assertEqual(p1.addr.width, 2)
 128         self.assertEqual(p1.data.width, 8)
 129         self.assertEqual(p1.en.width, 1)
 130         p2 = DummyPort(width=8, addr_bits=2, granularity=2)
 131         self.assertEqual(p2.en.width, 4)