nmigen/test/test_hdl_mem.py

   1 # nmigen: UnusedElaboratable=no
   2
   3 from ..hdl.ast import *
   4 from ..hdl.mem import *
   5 from .utils import *
   6
   7
   8 class MemoryTestCase(FHDLTestCase):
   9     def test_name(self):
  10         m1 = Memory(width=8, depth=4)
  11         self.assertEqual(m1.name, "m1")
  12         m2 = [Memory(width=8, depth=4)][0]
  13         self.assertEqual(m2.name, "$memory")
  14         m3 = Memory(width=8, depth=4, name="foo")
  15         self.assertEqual(m3.name, "foo")
  16
  17     def test_geometry(self):
  18         m = Memory(width=8, depth=4)
  19         self.assertEqual(m.width, 8)
  20         self.assertEqual(m.depth, 4)
  21
  22     def test_geometry_wrong(self):
  23         with self.assertRaises(TypeError,
  24                 msg="Memory width must be a non-negative integer, not -1"):
  25             m = Memory(width=-1, depth=4)
  26         with self.assertRaises(TypeError,
  27                 msg="Memory depth must be a non-negative integer, not -1"):
  28             m = Memory(width=8, depth=-1)
  29
  30     def test_init(self):
  31         m = Memory(width=8, depth=4, init=range(4))
  32         self.assertEqual(m.init, [0, 1, 2, 3])
  33
  34     def test_init_wrong_count(self):
  35         with self.assertRaises(ValueError,
  36                 msg="Memory initialization value count exceed memory depth (8 > 4)"):
  37             m = Memory(width=8, depth=4, init=range(8))
  38
  39     def test_init_wrong_type(self):
  40         with self.assertRaises(TypeError,
  41                 msg="Memory initialization value at address 1: "
  42                     "'str' object cannot be interpreted as an integer"):
  43             m = Memory(width=8, depth=4, init=[1, "0"])
  44
  45     def test_read_port_transparent(self):
  46         mem    = Memory(width=8, depth=4)
  47         rdport = mem.read_port()
  48         self.assertEqual(rdport.memory, mem)
  49         self.assertEqual(rdport.domain, "sync")
  50         self.assertEqual(rdport.transparent, True)
  51         self.assertEqual(len(rdport.addr), 2)
  52         self.assertEqual(len(rdport.data), 8)
  53         self.assertEqual(len(rdport.en), 1)
  54         self.assertIsInstance(rdport.en, Const)
  55         self.assertEqual(rdport.en.value, 1)
  56
  57     def test_read_port_non_transparent(self):
  58         mem    = Memory(width=8, depth=4)
  59         rdport = mem.read_port(transparent=False)
  60         self.assertEqual(rdport.memory, mem)
  61         self.assertEqual(rdport.domain, "sync")
  62         self.assertEqual(rdport.transparent, False)
  63         self.assertEqual(len(rdport.en), 1)
  64         self.assertIsInstance(rdport.en, Signal)
  65         self.assertEqual(rdport.en.reset, 1)
  66
  67     def test_read_port_asynchronous(self):
  68         mem    = Memory(width=8, depth=4)
  69         rdport = mem.read_port(domain="comb")
  70         self.assertEqual(rdport.memory, mem)
  71         self.assertEqual(rdport.domain, "comb")
  72         self.assertEqual(rdport.transparent, True)
  73         self.assertEqual(len(rdport.en), 1)
  74         self.assertIsInstance(rdport.en, Const)
  75         self.assertEqual(rdport.en.value, 1)
  76
  77     def test_read_port_wrong(self):
  78         mem = Memory(width=8, depth=4)
  79         with self.assertRaises(ValueError,
  80                 msg="Read port cannot be simultaneously asynchronous and non-transparent"):
  81             mem.read_port(domain="comb", transparent=False)
  82
  83     def test_write_port(self):
  84         mem    = Memory(width=8, depth=4)
  85         wrport = mem.write_port()
  86         self.assertEqual(wrport.memory, mem)
  87         self.assertEqual(wrport.domain, "sync")
  88         self.assertEqual(wrport.granularity, 8)
  89         self.assertEqual(len(wrport.addr), 2)
  90         self.assertEqual(len(wrport.data), 8)
  91         self.assertEqual(len(wrport.en), 1)
  92
  93     def test_write_port_granularity(self):
  94         mem    = Memory(width=8, depth=4)
  95         wrport = mem.write_port(granularity=2)
  96         self.assertEqual(wrport.memory, mem)
  97         self.assertEqual(wrport.domain, "sync")
  98         self.assertEqual(wrport.granularity, 2)
  99         self.assertEqual(len(wrport.addr), 2)
 100         self.assertEqual(len(wrport.data), 8)
 101         self.assertEqual(len(wrport.en), 4)
 102
 103     def test_write_port_granularity_wrong(self):
 104         mem = Memory(width=8, depth=4)
 105         with self.assertRaises(TypeError,
 106                 msg="Write port granularity must be a non-negative integer, not -1"):
 107             mem.write_port(granularity=-1)
 108         with self.assertRaises(ValueError,
 109                 msg="Write port granularity must not be greater than memory width (10 > 8)"):
 110             mem.write_port(granularity=10)
 111         with self.assertRaises(ValueError,
 112                 msg="Write port granularity must divide memory width evenly"):
 113             mem.write_port(granularity=3)
 114
 115
 116 class DummyPortTestCase(FHDLTestCase):
 117     def test_name(self):
 118         p1 = DummyPort(data_width=8, addr_width=2)
 119         self.assertEqual(p1.addr.name, "p1_addr")
 120         p2 = [DummyPort(data_width=8, addr_width=2)][0]
 121         self.assertEqual(p2.addr.name, "dummy_addr")
 122         p3 = DummyPort(data_width=8, addr_width=2, name="foo")
 123         self.assertEqual(p3.addr.name, "foo_addr")
 124
 125     def test_sizes(self):
 126         p1 = DummyPort(data_width=8, addr_width=2)
 127         self.assertEqual(p1.addr.width, 2)
 128         self.assertEqual(p1.data.width, 8)
 129         self.assertEqual(p1.en.width, 1)
 130         p2 = DummyPort(data_width=8, addr_width=2, granularity=2)
 131         self.assertEqual(p2.en.width, 4)