hdl.rec: improve repr() for Layout.
[nmigen.git] / nmigen / test / test_lib_io.py
1 from .utils import *
2 from ..hdl import *
3 from ..hdl.rec import *
4 from ..back.pysim import *
5 from ..lib.io import *
6
7
8 class PinLayoutCombTestCase(FHDLTestCase):
9 def test_pin_layout_i(self):
10 layout_1 = pin_layout(1, dir="i")
11 self.assertEqual(layout_1.fields, {
12 "i": ((1, False), DIR_NONE),
13 })
14
15 layout_2 = pin_layout(2, dir="i")
16 self.assertEqual(layout_2.fields, {
17 "i": ((2, False), DIR_NONE),
18 })
19
20 def test_pin_layout_o(self):
21 layout_1 = pin_layout(1, dir="o")
22 self.assertEqual(layout_1.fields, {
23 "o": ((1, False), DIR_NONE),
24 })
25
26 layout_2 = pin_layout(2, dir="o")
27 self.assertEqual(layout_2.fields, {
28 "o": ((2, False), DIR_NONE),
29 })
30
31 def test_pin_layout_oe(self):
32 layout_1 = pin_layout(1, dir="oe")
33 self.assertEqual(layout_1.fields, {
34 "o": ((1, False), DIR_NONE),
35 "oe": ((1, False), DIR_NONE),
36 })
37
38 layout_2 = pin_layout(2, dir="oe")
39 self.assertEqual(layout_2.fields, {
40 "o": ((2, False), DIR_NONE),
41 "oe": ((1, False), DIR_NONE),
42 })
43
44 def test_pin_layout_io(self):
45 layout_1 = pin_layout(1, dir="io")
46 self.assertEqual(layout_1.fields, {
47 "i": ((1, False), DIR_NONE),
48 "o": ((1, False), DIR_NONE),
49 "oe": ((1, False), DIR_NONE),
50 })
51
52 layout_2 = pin_layout(2, dir="io")
53 self.assertEqual(layout_2.fields, {
54 "i": ((2, False), DIR_NONE),
55 "o": ((2, False), DIR_NONE),
56 "oe": ((1, False), DIR_NONE),
57 })
58
59
60 class PinLayoutSDRTestCase(FHDLTestCase):
61 def test_pin_layout_i(self):
62 layout_1 = pin_layout(1, dir="i", xdr=1)
63 self.assertEqual(layout_1.fields, {
64 "i_clk": ((1, False), DIR_NONE),
65 "i": ((1, False), DIR_NONE),
66 })
67
68 layout_2 = pin_layout(2, dir="i", xdr=1)
69 self.assertEqual(layout_2.fields, {
70 "i_clk": ((1, False), DIR_NONE),
71 "i": ((2, False), DIR_NONE),
72 })
73
74 def test_pin_layout_o(self):
75 layout_1 = pin_layout(1, dir="o", xdr=1)
76 self.assertEqual(layout_1.fields, {
77 "o_clk": ((1, False), DIR_NONE),
78 "o": ((1, False), DIR_NONE),
79 })
80
81 layout_2 = pin_layout(2, dir="o", xdr=1)
82 self.assertEqual(layout_2.fields, {
83 "o_clk": ((1, False), DIR_NONE),
84 "o": ((2, False), DIR_NONE),
85 })
86
87 def test_pin_layout_oe(self):
88 layout_1 = pin_layout(1, dir="oe", xdr=1)
89 self.assertEqual(layout_1.fields, {
90 "o_clk": ((1, False), DIR_NONE),
91 "o": ((1, False), DIR_NONE),
92 "oe": ((1, False), DIR_NONE),
93 })
94
95 layout_2 = pin_layout(2, dir="oe", xdr=1)
96 self.assertEqual(layout_2.fields, {
97 "o_clk": ((1, False), DIR_NONE),
98 "o": ((2, False), DIR_NONE),
99 "oe": ((1, False), DIR_NONE),
100 })
101
102 def test_pin_layout_io(self):
103 layout_1 = pin_layout(1, dir="io", xdr=1)
104 self.assertEqual(layout_1.fields, {
105 "i_clk": ((1, False), DIR_NONE),
106 "i": ((1, False), DIR_NONE),
107 "o_clk": ((1, False), DIR_NONE),
108 "o": ((1, False), DIR_NONE),
109 "oe": ((1, False), DIR_NONE),
110 })
111
112 layout_2 = pin_layout(2, dir="io", xdr=1)
113 self.assertEqual(layout_2.fields, {
114 "i_clk": ((1, False), DIR_NONE),
115 "i": ((2, False), DIR_NONE),
116 "o_clk": ((1, False), DIR_NONE),
117 "o": ((2, False), DIR_NONE),
118 "oe": ((1, False), DIR_NONE),
119 })
120
121
122 class PinLayoutDDRTestCase(FHDLTestCase):
123 def test_pin_layout_i(self):
124 layout_1 = pin_layout(1, dir="i", xdr=2)
125 self.assertEqual(layout_1.fields, {
126 "i_clk": ((1, False), DIR_NONE),
127 "i0": ((1, False), DIR_NONE),
128 "i1": ((1, False), DIR_NONE),
129 })
130
131 layout_2 = pin_layout(2, dir="i", xdr=2)
132 self.assertEqual(layout_2.fields, {
133 "i_clk": ((1, False), DIR_NONE),
134 "i0": ((2, False), DIR_NONE),
135 "i1": ((2, False), DIR_NONE),
136 })
137
138 def test_pin_layout_o(self):
139 layout_1 = pin_layout(1, dir="o", xdr=2)
140 self.assertEqual(layout_1.fields, {
141 "o_clk": ((1, False), DIR_NONE),
142 "o0": ((1, False), DIR_NONE),
143 "o1": ((1, False), DIR_NONE),
144 })
145
146 layout_2 = pin_layout(2, dir="o", xdr=2)
147 self.assertEqual(layout_2.fields, {
148 "o_clk": ((1, False), DIR_NONE),
149 "o0": ((2, False), DIR_NONE),
150 "o1": ((2, False), DIR_NONE),
151 })
152
153 def test_pin_layout_oe(self):
154 layout_1 = pin_layout(1, dir="oe", xdr=2)
155 self.assertEqual(layout_1.fields, {
156 "o_clk": ((1, False), DIR_NONE),
157 "o0": ((1, False), DIR_NONE),
158 "o1": ((1, False), DIR_NONE),
159 "oe": ((1, False), DIR_NONE),
160 })
161
162 layout_2 = pin_layout(2, dir="oe", xdr=2)
163 self.assertEqual(layout_2.fields, {
164 "o_clk": ((1, False), DIR_NONE),
165 "o0": ((2, False), DIR_NONE),
166 "o1": ((2, False), DIR_NONE),
167 "oe": ((1, False), DIR_NONE),
168 })
169
170 def test_pin_layout_io(self):
171 layout_1 = pin_layout(1, dir="io", xdr=2)
172 self.assertEqual(layout_1.fields, {
173 "i_clk": ((1, False), DIR_NONE),
174 "i0": ((1, False), DIR_NONE),
175 "i1": ((1, False), DIR_NONE),
176 "o_clk": ((1, False), DIR_NONE),
177 "o0": ((1, False), DIR_NONE),
178 "o1": ((1, False), DIR_NONE),
179 "oe": ((1, False), DIR_NONE),
180 })
181
182 layout_2 = pin_layout(2, dir="io", xdr=2)
183 self.assertEqual(layout_2.fields, {
184 "i_clk": ((1, False), DIR_NONE),
185 "i0": ((2, False), DIR_NONE),
186 "i1": ((2, False), DIR_NONE),
187 "o_clk": ((1, False), DIR_NONE),
188 "o0": ((2, False), DIR_NONE),
189 "o1": ((2, False), DIR_NONE),
190 "oe": ((1, False), DIR_NONE),
191 })
192
193
194 class PinTestCase(FHDLTestCase):
195 def test_attributes(self):
196 pin = Pin(2, dir="io", xdr=2)
197 self.assertEqual(pin.width, 2)
198 self.assertEqual(pin.dir, "io")
199 self.assertEqual(pin.xdr, 2)