nmigen/test/test_sim.py

   1 from contextlib import contextmanager
   2
   3 from .tools import *
   4 from ..tools import flatten, union
   5 from ..hdl.ast import *
   6 from ..hdl.cd import  *
   7 from ..hdl.mem import *
   8 from ..hdl.rec import *
   9 from ..hdl.dsl import  *
  10 from ..hdl.ir import *
  11 from ..back.pysim import *
  12
  13
  14 class SimulatorUnitTestCase(FHDLTestCase):
  15     def assertStatement(self, stmt, inputs, output, reset=0):
  16         inputs = [Value.wrap(i) for i in inputs]
  17         output = Value.wrap(output)
  18
  19         isigs = [Signal(i.shape(), name=n) for i, n in zip(inputs, "abcd")]
  20         osig  = Signal(output.shape(), name="y", reset=reset)
  21
  22         stmt = stmt(osig, *isigs)
  23         frag = Fragment()
  24         frag.add_statements(stmt)
  25         for signal in flatten(s._lhs_signals() for s in Statement.wrap(stmt)):
  26             frag.add_driver(signal)
  27
  28         with Simulator(frag,
  29                 vcd_file =open("test.vcd",  "w"),
  30                 gtkw_file=open("test.gtkw", "w"),
  31                 traces=[*isigs, osig]) as sim:
  32             def process():
  33                 for isig, input in zip(isigs, inputs):
  34                     yield isig.eq(input)
  35                 yield Delay()
  36                 self.assertEqual((yield osig), output.value)
  37             sim.add_process(process)
  38             sim.run()
  39
  40     def test_invert(self):
  41         stmt = lambda y, a: y.eq(~a)
  42         self.assertStatement(stmt, [C(0b0000, 4)], C(0b1111, 4))
  43         self.assertStatement(stmt, [C(0b1010, 4)], C(0b0101, 4))
  44         self.assertStatement(stmt, [C(0,      4)], C(-1,     4))
  45
  46     def test_neg(self):
  47         stmt = lambda y, a: y.eq(-a)
  48         self.assertStatement(stmt, [C(0b0000, 4)], C(0b0000, 4))
  49         self.assertStatement(stmt, [C(0b0001, 4)], C(0b1111, 4))
  50         self.assertStatement(stmt, [C(0b1010, 4)], C(0b0110, 4))
  51         self.assertStatement(stmt, [C(1,      4)], C(-1,     4))
  52         self.assertStatement(stmt, [C(5,      4)], C(-5,     4))
  53
  54     def test_bool(self):
  55         stmt = lambda y, a: y.eq(a.bool())
  56         self.assertStatement(stmt, [C(0, 4)], C(0))
  57         self.assertStatement(stmt, [C(1, 4)], C(1))
  58         self.assertStatement(stmt, [C(2, 4)], C(1))
  59
  60     def test_any(self):
  61         stmt = lambda y, a: y.eq(a.any())
  62         self.assertStatement(stmt, [C(0b00, 2)], C(0))
  63         self.assertStatement(stmt, [C(0b01, 2)], C(1))
  64         self.assertStatement(stmt, [C(0b10, 2)], C(1))
  65         self.assertStatement(stmt, [C(0b11, 2)], C(1))
  66
  67     def test_all(self):
  68         stmt = lambda y, a: y.eq(a.all())
  69         self.assertStatement(stmt, [C(0b00, 2)], C(0))
  70         self.assertStatement(stmt, [C(0b01, 2)], C(0))
  71         self.assertStatement(stmt, [C(0b10, 2)], C(0))
  72         self.assertStatement(stmt, [C(0b11, 2)], C(1))
  73
  74     def test_xor_unary(self):
  75         stmt = lambda y, a: y.eq(a.xor())
  76         self.assertStatement(stmt, [C(0b00, 2)], C(0))
  77         self.assertStatement(stmt, [C(0b01, 2)], C(1))
  78         self.assertStatement(stmt, [C(0b10, 2)], C(1))
  79         self.assertStatement(stmt, [C(0b11, 2)], C(0))
  80
  81     def test_add(self):
  82         stmt = lambda y, a, b: y.eq(a + b)
  83         self.assertStatement(stmt, [C(0,  4), C(1,  4)], C(1,   4))
  84         self.assertStatement(stmt, [C(-5, 4), C(-5, 4)], C(-10, 5))
  85
  86     def test_sub(self):
  87         stmt = lambda y, a, b: y.eq(a - b)
  88         self.assertStatement(stmt, [C(2,  4), C(1,  4)], C(1,   4))
  89         self.assertStatement(stmt, [C(0,  4), C(1,  4)], C(-1,  4))
  90         self.assertStatement(stmt, [C(0,  4), C(10, 4)], C(-10, 5))
  91
  92     def test_mul(self):
  93         stmt = lambda y, a, b: y.eq(a * b)
  94         self.assertStatement(stmt, [C(2,  4), C(1,  4)], C(2,   8))
  95         self.assertStatement(stmt, [C(2,  4), C(2,  4)], C(4,   8))
  96         self.assertStatement(stmt, [C(7,  4), C(7,  4)], C(49,  8))
  97
  98     def test_and(self):
  99         stmt = lambda y, a, b: y.eq(a & b)
 100         self.assertStatement(stmt, [C(0b1100, 4), C(0b1010, 4)], C(0b1000, 4))
 101
 102     def test_or(self):
 103         stmt = lambda y, a, b: y.eq(a | b)
 104         self.assertStatement(stmt, [C(0b1100, 4), C(0b1010, 4)], C(0b1110, 4))
 105
 106     def test_xor_binary(self):
 107         stmt = lambda y, a, b: y.eq(a ^ b)
 108         self.assertStatement(stmt, [C(0b1100, 4), C(0b1010, 4)], C(0b0110, 4))
 109
 110     def test_shl(self):
 111         stmt = lambda y, a, b: y.eq(a << b)
 112         self.assertStatement(stmt, [C(0b1001, 4), C(0)],  C(0b1001,    5))
 113         self.assertStatement(stmt, [C(0b1001, 4), C(3)],  C(0b1001000, 7))
 114         self.assertStatement(stmt, [C(0b1001, 4), C(-2)], C(0b10,      7))
 115
 116     def test_shr(self):
 117         stmt = lambda y, a, b: y.eq(a >> b)
 118         self.assertStatement(stmt, [C(0b1001, 4), C(0)],  C(0b1001,    4))
 119         self.assertStatement(stmt, [C(0b1001, 4), C(2)],  C(0b10,      4))
 120         self.assertStatement(stmt, [C(0b1001, 4), C(-2)], C(0b100100,  5))
 121
 122     def test_eq(self):
 123         stmt = lambda y, a, b: y.eq(a == b)
 124         self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(1))
 125         self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(0))
 126         self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(0))
 127
 128     def test_ne(self):
 129         stmt = lambda y, a, b: y.eq(a != b)
 130         self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(0))
 131         self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(1))
 132         self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(1))
 133
 134     def test_lt(self):
 135         stmt = lambda y, a, b: y.eq(a < b)
 136         self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(0))
 137         self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(1))
 138         self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(0))
 139
 140     def test_ge(self):
 141         stmt = lambda y, a, b: y.eq(a >= b)
 142         self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(1))
 143         self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(0))
 144         self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(1))
 145
 146     def test_gt(self):
 147         stmt = lambda y, a, b: y.eq(a > b)
 148         self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(0))
 149         self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(0))
 150         self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(1))
 151
 152     def test_le(self):
 153         stmt = lambda y, a, b: y.eq(a <= b)
 154         self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(1))
 155         self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(1))
 156         self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(0))
 157
 158     def test_mux(self):
 159         stmt = lambda y, a, b, c: y.eq(Mux(c, a, b))
 160         self.assertStatement(stmt, [C(2, 4), C(3, 4), C(0)], C(3, 4))
 161         self.assertStatement(stmt, [C(2, 4), C(3, 4), C(1)], C(2, 4))
 162
 163     def test_slice(self):
 164         stmt1 = lambda y, a: y.eq(a[2])
 165         self.assertStatement(stmt1, [C(0b10110100, 8)], C(0b1,  1))
 166         stmt2 = lambda y, a: y.eq(a[2:4])
 167         self.assertStatement(stmt2, [C(0b10110100, 8)], C(0b01, 2))
 168
 169     def test_slice_lhs(self):
 170         stmt1 = lambda y, a: y[2].eq(a)
 171         self.assertStatement(stmt1, [C(0b0,  1)], C(0b11111011, 8), reset=0b11111111)
 172         stmt2 = lambda y, a: y[2:4].eq(a)
 173         self.assertStatement(stmt2, [C(0b01, 2)], C(0b11110111, 8), reset=0b11111011)
 174
 175     def test_bit_select(self):
 176         stmt = lambda y, a, b: y.eq(a.bit_select(b, 3))
 177         self.assertStatement(stmt, [C(0b10110100, 8), C(0)], C(0b100, 3))
 178         self.assertStatement(stmt, [C(0b10110100, 8), C(2)], C(0b101, 3))
 179         self.assertStatement(stmt, [C(0b10110100, 8), C(3)], C(0b110, 3))
 180
 181     def test_bit_select_lhs(self):
 182         stmt = lambda y, a, b: y.bit_select(a, 3).eq(b)
 183         self.assertStatement(stmt, [C(0), C(0b100, 3)], C(0b11111100, 8), reset=0b11111111)
 184         self.assertStatement(stmt, [C(2), C(0b101, 3)], C(0b11110111, 8), reset=0b11111111)
 185         self.assertStatement(stmt, [C(3), C(0b110, 3)], C(0b11110111, 8), reset=0b11111111)
 186
 187     def test_word_select(self):
 188         stmt = lambda y, a, b: y.eq(a.word_select(b, 3))
 189         self.assertStatement(stmt, [C(0b10110100, 8), C(0)], C(0b100, 3))
 190         self.assertStatement(stmt, [C(0b10110100, 8), C(1)], C(0b110, 3))
 191         self.assertStatement(stmt, [C(0b10110100, 8), C(2)], C(0b010, 3))
 192
 193     def test_word_select_lhs(self):
 194         stmt = lambda y, a, b: y.word_select(a, 3).eq(b)
 195         self.assertStatement(stmt, [C(0), C(0b100, 3)], C(0b11111100, 8), reset=0b11111111)
 196         self.assertStatement(stmt, [C(1), C(0b101, 3)], C(0b11101111, 8), reset=0b11111111)
 197         self.assertStatement(stmt, [C(2), C(0b110, 3)], C(0b10111111, 8), reset=0b11111111)
 198
 199     def test_cat(self):
 200         stmt = lambda y, *xs: y.eq(Cat(*xs))
 201         self.assertStatement(stmt, [C(0b10, 2), C(0b01, 2)], C(0b0110, 4))
 202
 203     def test_cat_lhs(self):
 204         l = Signal(3)
 205         m = Signal(3)
 206         n = Signal(3)
 207         stmt = lambda y, a: [Cat(l, m, n).eq(a), y.eq(Cat(n, m, l))]
 208         self.assertStatement(stmt, [C(0b100101110, 9)], C(0b110101100, 9))
 209
 210     def test_record(self):
 211         rec = Record([
 212             ("l", 1),
 213             ("m", 2),
 214         ])
 215         stmt = lambda y, a: [rec.eq(a), y.eq(rec)]
 216         self.assertStatement(stmt, [C(0b101, 3)], C(0b101, 3))
 217
 218     def test_repl(self):
 219         stmt = lambda y, a: y.eq(Repl(a, 3))
 220         self.assertStatement(stmt, [C(0b10, 2)], C(0b101010, 6))
 221
 222     def test_array(self):
 223         array = Array([1, 4, 10])
 224         stmt = lambda y, a: y.eq(array[a])
 225         self.assertStatement(stmt, [C(0)], C(1))
 226         self.assertStatement(stmt, [C(1)], C(4))
 227         self.assertStatement(stmt, [C(2)], C(10))
 228
 229     def test_array_oob(self):
 230         array = Array([1, 4, 10])
 231         stmt = lambda y, a: y.eq(array[a])
 232         self.assertStatement(stmt, [C(3)], C(10))
 233         self.assertStatement(stmt, [C(4)], C(10))
 234
 235     def test_array_lhs(self):
 236         l = Signal(3, reset=1)
 237         m = Signal(3, reset=4)
 238         n = Signal(3, reset=7)
 239         array = Array([l, m, n])
 240         stmt = lambda y, a, b: [array[a].eq(b), y.eq(Cat(*array))]
 241         self.assertStatement(stmt, [C(0), C(0b000)], C(0b111100000))
 242         self.assertStatement(stmt, [C(1), C(0b010)], C(0b111010001))
 243         self.assertStatement(stmt, [C(2), C(0b100)], C(0b100100001))
 244
 245     def test_array_lhs_oob(self):
 246         l = Signal(3)
 247         m = Signal(3)
 248         n = Signal(3)
 249         array = Array([l, m, n])
 250         stmt = lambda y, a, b: [array[a].eq(b), y.eq(Cat(*array))]
 251         self.assertStatement(stmt, [C(3), C(0b001)], C(0b001000000))
 252         self.assertStatement(stmt, [C(4), C(0b010)], C(0b010000000))
 253
 254     def test_array_index(self):
 255         array = Array(Array(x * y for y in range(10)) for x in range(10))
 256         stmt = lambda y, a, b: y.eq(array[a][b])
 257         for x in range(10):
 258             for y in range(10):
 259                 self.assertStatement(stmt, [C(x), C(y)], C(x * y))
 260
 261     def test_array_attr(self):
 262         from collections import namedtuple
 263         pair = namedtuple("pair", ("p", "n"))
 264
 265         array = Array(pair(x, -x) for x in range(10))
 266         stmt = lambda y, a: y.eq(array[a].p + array[a].n)
 267         for i in range(10):
 268             self.assertStatement(stmt, [C(i)], C(0))
 269
 270
 271 class SimulatorIntegrationTestCase(FHDLTestCase):
 272     @contextmanager
 273     def assertSimulation(self, module, deadline=None):
 274         with Simulator(module) as sim:
 275             yield sim
 276             if deadline is None:
 277                 sim.run()
 278             else:
 279                 sim.run_until(deadline)
 280
 281     def setUp_counter(self):
 282         self.count = Signal(3, reset=4)
 283         self.sync  = ClockDomain()
 284
 285         self.m = Module()
 286         self.m.d.sync  += self.count.eq(self.count + 1)
 287         self.m.domains += self.sync
 288
 289     def test_counter_process(self):
 290         self.setUp_counter()
 291         with self.assertSimulation(self.m) as sim:
 292             def process():
 293                 self.assertEqual((yield self.count), 4)
 294                 yield Delay(1e-6)
 295                 self.assertEqual((yield self.count), 4)
 296                 yield self.sync.clk.eq(1)
 297                 self.assertEqual((yield self.count), 5)
 298                 yield Delay(1e-6)
 299                 self.assertEqual((yield self.count), 5)
 300                 yield self.sync.clk.eq(0)
 301                 self.assertEqual((yield self.count), 5)
 302                 for _ in range(3):
 303                     yield Delay(1e-6)
 304                     yield self.sync.clk.eq(1)
 305                     yield Delay(1e-6)
 306                     yield self.sync.clk.eq(0)
 307                 self.assertEqual((yield self.count), 0)
 308             sim.add_process(process)
 309
 310     def test_counter_clock_and_sync_process(self):
 311         self.setUp_counter()
 312         with self.assertSimulation(self.m) as sim:
 313             sim.add_clock(1e-6, domain="sync")
 314             def process():
 315                 self.assertEqual((yield self.count), 4)
 316                 self.assertEqual((yield self.sync.clk), 1)
 317                 yield
 318                 self.assertEqual((yield self.count), 5)
 319                 self.assertEqual((yield self.sync.clk), 1)
 320                 for _ in range(3):
 321                     yield
 322                 self.assertEqual((yield self.count), 0)
 323             sim.add_sync_process(process)
 324
 325     def setUp_alu(self):
 326         self.a = Signal(8)
 327         self.b = Signal(8)
 328         self.o = Signal(8)
 329         self.x = Signal(8)
 330         self.s = Signal(2)
 331         self.sync = ClockDomain(reset_less=True)
 332
 333         self.m = Module()
 334         self.m.d.comb += self.x.eq(self.a ^ self.b)
 335         with self.m.Switch(self.s):
 336             with self.m.Case(0):
 337                 self.m.d.sync += self.o.eq(self.a + self.b)
 338             with self.m.Case(1):
 339                 self.m.d.sync += self.o.eq(self.a - self.b)
 340             with self.m.Case():
 341                 self.m.d.sync += self.o.eq(0)
 342         self.m.domains += self.sync
 343
 344     def test_alu(self):
 345         self.setUp_alu()
 346         with self.assertSimulation(self.m) as sim:
 347             sim.add_clock(1e-6)
 348             def process():
 349                 yield self.a.eq(5)
 350                 yield self.b.eq(1)
 351                 yield
 352                 self.assertEqual((yield self.x), 4)
 353                 yield
 354                 self.assertEqual((yield self.o), 6)
 355                 yield self.s.eq(1)
 356                 yield
 357                 yield
 358                 self.assertEqual((yield self.o), 4)
 359                 yield self.s.eq(2)
 360                 yield
 361                 yield
 362                 self.assertEqual((yield self.o), 0)
 363             sim.add_sync_process(process)
 364
 365     def setUp_multiclock(self):
 366         self.sys = ClockDomain()
 367         self.pix = ClockDomain()
 368
 369         self.m = Module()
 370         self.m.domains += self.sys, self.pix
 371
 372     def test_multiclock(self):
 373         self.setUp_multiclock()
 374         with self.assertSimulation(self.m) as sim:
 375             sim.add_clock(1e-6, domain="sys")
 376             sim.add_clock(0.3e-6, domain="pix")
 377
 378             def sys_process():
 379                 yield Passive()
 380                 yield
 381                 yield
 382                 self.fail()
 383             def pix_process():
 384                 yield
 385                 yield
 386                 yield
 387             sim.add_sync_process(sys_process, domain="sys")
 388             sim.add_sync_process(pix_process, domain="pix")
 389
 390     def setUp_lhs_rhs(self):
 391         self.i = Signal(8)
 392         self.o = Signal(8)
 393
 394         self.m = Module()
 395         self.m.d.comb += self.o.eq(self.i)
 396
 397     def test_complex_lhs_rhs(self):
 398         self.setUp_lhs_rhs()
 399         with self.assertSimulation(self.m) as sim:
 400             def process():
 401                 yield self.i.eq(0b10101010)
 402                 yield self.i[:4].eq(-1)
 403                 yield Delay()
 404                 self.assertEqual((yield self.i[:4]), 0b1111)
 405                 self.assertEqual((yield self.i), 0b10101111)
 406             sim.add_process(process)
 407
 408     def test_run_until(self):
 409         m = Module()
 410         s = Signal()
 411         m.d.sync += s.eq(0)
 412         with self.assertSimulation(m, deadline=100e-6) as sim:
 413             sim.add_clock(1e-6)
 414             def process():
 415                 for _ in range(101):
 416                     yield Delay(1e-6)
 417                 self.fail()
 418             sim.add_process(process)
 419
 420     def test_add_process_wrong(self):
 421         with self.assertSimulation(Module()) as sim:
 422             with self.assertRaises(TypeError,
 423                     msg="Cannot add a process '1' because it is not a generator or "
 424                         "a generator function"):
 425                 sim.add_process(1)
 426
 427     def test_add_clock_wrong_twice(self):
 428         m = Module()
 429         s = Signal()
 430         m.d.sync += s.eq(0)
 431         with self.assertSimulation(m) as sim:
 432             sim.add_clock(1)
 433             with self.assertRaises(ValueError,
 434                     msg="Domain 'sync' already has a clock driving it"):
 435                 sim.add_clock(1)
 436
 437     def test_add_clock_wrong_missing(self):
 438         m = Module()
 439         with self.assertSimulation(m) as sim:
 440             with self.assertRaises(ValueError,
 441                     msg="Domain 'sync' is not present in simulation"):
 442                 sim.add_clock(1)
 443
 444     def test_add_clock_if_exists(self):
 445         m = Module()
 446         with self.assertSimulation(m) as sim:
 447             sim.add_clock(1, if_exists=True)
 448
 449     def test_eq_signal_unused_wrong(self):
 450         self.setUp_lhs_rhs()
 451         self.s = Signal()
 452         with self.assertSimulation(self.m) as sim:
 453             def process():
 454                 with self.assertRaisesRegex(ValueError,
 455                         regex=r"Process '.+?' sent a request to set signal '\(sig s\)', "
 456                               r"which is not a part of simulation"):
 457                     yield self.s.eq(0)
 458                 yield Delay()
 459             sim.add_process(process)
 460
 461     def test_eq_signal_comb_wrong(self):
 462         self.setUp_lhs_rhs()
 463         with self.assertSimulation(self.m) as sim:
 464             def process():
 465                 with self.assertRaisesRegex(ValueError,
 466                         regex=r"Process '.+?' sent a request to set signal '\(sig o\)', "
 467                               r"which is a part of combinatorial assignment in simulation"):
 468                     yield self.o.eq(0)
 469                 yield Delay()
 470             sim.add_process(process)
 471
 472     def test_command_wrong(self):
 473         with self.assertSimulation(Module()) as sim:
 474             def process():
 475                 with self.assertRaisesRegex(TypeError,
 476                         regex=r"Received unsupported command '1' from process '.+?'"):
 477                     yield 1
 478                 yield Delay()
 479             sim.add_process(process)
 480
 481     def setUp_memory(self, rd_synchronous=True, rd_transparent=True, wr_granularity=None):
 482         self.m = Module()
 483         self.memory = Memory(width=8, depth=4, init=[0xaa, 0x55])
 484         self.m.submodules.rdport = self.rdport = \
 485             self.memory.read_port(domain="sync" if rd_synchronous else "comb",
 486                                   transparent=rd_transparent)
 487         self.m.submodules.wrport = self.wrport = \
 488             self.memory.write_port(granularity=wr_granularity)
 489
 490     def test_memory_init(self):
 491         self.setUp_memory()
 492         with self.assertSimulation(self.m) as sim:
 493             def process():
 494                 self.assertEqual((yield self.rdport.data), 0xaa)
 495                 yield self.rdport.addr.eq(1)
 496                 yield
 497                 yield
 498                 self.assertEqual((yield self.rdport.data), 0x55)
 499                 yield self.rdport.addr.eq(2)
 500                 yield
 501                 yield
 502                 self.assertEqual((yield self.rdport.data), 0x00)
 503             sim.add_clock(1e-6)
 504             sim.add_sync_process(process)
 505
 506     def test_memory_write(self):
 507         self.setUp_memory()
 508         with self.assertSimulation(self.m) as sim:
 509             def process():
 510                 yield self.wrport.addr.eq(4)
 511                 yield self.wrport.data.eq(0x33)
 512                 yield self.wrport.en.eq(1)
 513                 yield
 514                 yield self.wrport.en.eq(0)
 515                 yield self.rdport.addr.eq(4)
 516                 yield
 517                 self.assertEqual((yield self.rdport.data), 0x33)
 518             sim.add_clock(1e-6)
 519             sim.add_sync_process(process)
 520
 521     def test_memory_write_granularity(self):
 522         self.setUp_memory(wr_granularity=4)
 523         with self.assertSimulation(self.m) as sim:
 524             def process():
 525                 yield self.wrport.data.eq(0x50)
 526                 yield self.wrport.en.eq(0b00)
 527                 yield
 528                 yield self.wrport.en.eq(0)
 529                 yield
 530                 self.assertEqual((yield self.rdport.data), 0xaa)
 531                 yield self.wrport.en.eq(0b10)
 532                 yield
 533                 yield self.wrport.en.eq(0)
 534                 yield
 535                 self.assertEqual((yield self.rdport.data), 0x5a)
 536                 yield self.wrport.data.eq(0x33)
 537                 yield self.wrport.en.eq(0b01)
 538                 yield
 539                 yield self.wrport.en.eq(0)
 540                 yield
 541                 self.assertEqual((yield self.rdport.data), 0x53)
 542             sim.add_clock(1e-6)
 543             sim.add_sync_process(process)
 544
 545     def test_memory_read_before_write(self):
 546         self.setUp_memory(rd_transparent=False)
 547         with self.assertSimulation(self.m) as sim:
 548             def process():
 549                 yield self.wrport.data.eq(0x33)
 550                 yield self.wrport.en.eq(1)
 551                 yield
 552                 self.assertEqual((yield self.rdport.data), 0xaa)
 553                 yield
 554                 self.assertEqual((yield self.rdport.data), 0xaa)
 555                 yield Delay(1e-6) # let comb propagate
 556                 self.assertEqual((yield self.rdport.data), 0x33)
 557             sim.add_clock(1e-6)
 558             sim.add_sync_process(process)
 559
 560     def test_memory_write_through(self):
 561         self.setUp_memory(rd_transparent=True)
 562         with self.assertSimulation(self.m) as sim:
 563             def process():
 564                 yield self.wrport.data.eq(0x33)
 565                 yield self.wrport.en.eq(1)
 566                 yield
 567                 self.assertEqual((yield self.rdport.data), 0xaa)
 568                 yield Delay(1e-6) # let comb propagate
 569                 self.assertEqual((yield self.rdport.data), 0x33)
 570                 yield
 571                 yield self.rdport.addr.eq(1)
 572                 yield Delay(1e-6) # let comb propagate
 573                 self.assertEqual((yield self.rdport.data), 0x33)
 574             sim.add_clock(1e-6)
 575             sim.add_sync_process(process)
 576
 577     def test_memory_async_read_write(self):
 578         self.setUp_memory(rd_synchronous=False)
 579         with self.assertSimulation(self.m) as sim:
 580             def process():
 581                 yield self.rdport.addr.eq(0)
 582                 yield Delay()
 583                 self.assertEqual((yield self.rdport.data), 0xaa)
 584                 yield self.rdport.addr.eq(1)
 585                 yield Delay()
 586                 self.assertEqual((yield self.rdport.data), 0x55)
 587                 yield self.rdport.addr.eq(0)
 588                 yield self.wrport.addr.eq(0)
 589                 yield self.wrport.data.eq(0x33)
 590                 yield self.wrport.en.eq(1)
 591                 yield Tick("sync")
 592                 self.assertEqual((yield self.rdport.data), 0xaa)
 593                 yield Delay(1e-6) # let comb propagate
 594                 self.assertEqual((yield self.rdport.data), 0x33)
 595             sim.add_clock(1e-6)
 596             sim.add_process(process)
 597
 598     def test_memory_read_only(self):
 599         self.m = Module()
 600         self.memory = Memory(width=8, depth=4, init=[0xaa, 0x55])
 601         self.m.submodules.rdport = self.rdport = self.memory.read_port()
 602         with self.assertSimulation(self.m) as sim:
 603             def process():
 604                 self.assertEqual((yield self.rdport.data), 0xaa)
 605                 yield self.rdport.addr.eq(1)
 606                 yield
 607                 yield
 608                 self.assertEqual((yield self.rdport.data), 0x55)
 609             sim.add_clock(1e-6)
 610             sim.add_sync_process(process)
 611
 612     def test_sample_helpers(self):
 613         m = Module()
 614         s = Signal(2)
 615         def mk(x):
 616             y = Signal.like(x)
 617             m.d.comb += y.eq(x)
 618             return y
 619         p0, r0, f0, s0 = mk(Past(s, 0)), mk(Rose(s)),    mk(Fell(s)),    mk(Stable(s))
 620         p1, r1, f1, s1 = mk(Past(s)),    mk(Rose(s, 1)), mk(Fell(s, 1)), mk(Stable(s, 1))
 621         p2, r2, f2, s2 = mk(Past(s, 2)), mk(Rose(s, 2)), mk(Fell(s, 2)), mk(Stable(s, 2))
 622         p3, r3, f3, s3 = mk(Past(s, 3)), mk(Rose(s, 3)), mk(Fell(s, 3)), mk(Stable(s, 3))
 623         with self.assertSimulation(m) as sim:
 624             def process_gen():
 625                 yield s.eq(0b10)
 626                 yield
 627                 yield
 628                 yield s.eq(0b01)
 629                 yield
 630             def process_check():
 631                 yield
 632                 yield
 633                 yield
 634
 635                 self.assertEqual((yield p0), 0b01)
 636                 self.assertEqual((yield p1), 0b10)
 637                 self.assertEqual((yield p2), 0b10)
 638                 self.assertEqual((yield p3), 0b00)
 639
 640                 self.assertEqual((yield s0), 0b0)
 641                 self.assertEqual((yield s1), 0b1)
 642                 self.assertEqual((yield s2), 0b0)
 643                 self.assertEqual((yield s3), 0b1)
 644
 645                 self.assertEqual((yield r0), 0b01)
 646                 self.assertEqual((yield r1), 0b00)
 647                 self.assertEqual((yield r2), 0b10)
 648                 self.assertEqual((yield r3), 0b00)
 649
 650                 self.assertEqual((yield f0), 0b10)
 651                 self.assertEqual((yield f1), 0b00)
 652                 self.assertEqual((yield f2), 0b00)
 653                 self.assertEqual((yield f3), 0b00)
 654             sim.add_clock(1e-6)
 655             sim.add_sync_process(process_gen)
 656             sim.add_sync_process(process_check)
 657
 658     def test_wrong_not_run(self):
 659         with self.assertWarns(UserWarning,
 660                 msg="Simulation created, but not run"):
 661             with Simulator(Fragment()) as sim:
 662                 pass