nmigen/test/test_sim.py

   1 from contextlib import contextmanager
   2
   3 from .tools import *
   4 from ..tools import flatten, union
   5 from ..hdl.ast import *
   6 from ..hdl.cd import  *
   7 from ..hdl.mem import *
   8 from ..hdl.rec import *
   9 from ..hdl.dsl import  *
  10 from ..hdl.ir import *
  11 from ..back.pysim import *
  12
  13
  14 class SimulatorUnitTestCase(FHDLTestCase):
  15     def assertStatement(self, stmt, inputs, output, reset=0):
  16         inputs = [Value.wrap(i) for i in inputs]
  17         output = Value.wrap(output)
  18
  19         isigs = [Signal(i.shape(), name=n) for i, n in zip(inputs, "abcd")]
  20         osig  = Signal(output.shape(), name="y", reset=reset)
  21
  22         stmt = stmt(osig, *isigs)
  23         frag = Fragment()
  24         frag.add_statements(stmt)
  25         for signal in flatten(s._lhs_signals() for s in Statement.wrap(stmt)):
  26             frag.add_driver(signal)
  27
  28         with Simulator(frag,
  29                 vcd_file =open("test.vcd",  "w"),
  30                 gtkw_file=open("test.gtkw", "w"),
  31                 traces=[*isigs, osig]) as sim:
  32             def process():
  33                 for isig, input in zip(isigs, inputs):
  34                     yield isig.eq(input)
  35                 yield Delay()
  36                 self.assertEqual((yield osig), output.value)
  37             sim.add_process(process)
  38             sim.run()
  39
  40     def test_invert(self):
  41         stmt = lambda y, a: y.eq(~a)
  42         self.assertStatement(stmt, [C(0b0000, 4)], C(0b1111, 4))
  43         self.assertStatement(stmt, [C(0b1010, 4)], C(0b0101, 4))
  44         self.assertStatement(stmt, [C(0,      4)], C(-1,     4))
  45
  46     def test_neg(self):
  47         stmt = lambda y, a: y.eq(-a)
  48         self.assertStatement(stmt, [C(0b0000, 4)], C(0b0000, 4))
  49         self.assertStatement(stmt, [C(0b0001, 4)], C(0b1111, 4))
  50         self.assertStatement(stmt, [C(0b1010, 4)], C(0b0110, 4))
  51         self.assertStatement(stmt, [C(1,      4)], C(-1,     4))
  52         self.assertStatement(stmt, [C(5,      4)], C(-5,     4))
  53
  54     def test_bool(self):
  55         stmt = lambda y, a: y.eq(a.bool())
  56         self.assertStatement(stmt, [C(0, 4)], C(0))
  57         self.assertStatement(stmt, [C(1, 4)], C(1))
  58         self.assertStatement(stmt, [C(2, 4)], C(1))
  59
  60     def test_add(self):
  61         stmt = lambda y, a, b: y.eq(a + b)
  62         self.assertStatement(stmt, [C(0,  4), C(1,  4)], C(1,   4))
  63         self.assertStatement(stmt, [C(-5, 4), C(-5, 4)], C(-10, 5))
  64
  65     def test_sub(self):
  66         stmt = lambda y, a, b: y.eq(a - b)
  67         self.assertStatement(stmt, [C(2,  4), C(1,  4)], C(1,   4))
  68         self.assertStatement(stmt, [C(0,  4), C(1,  4)], C(-1,  4))
  69         self.assertStatement(stmt, [C(0,  4), C(10, 4)], C(-10, 5))
  70
  71     def test_mul(self):
  72         stmt = lambda y, a, b: y.eq(a * b)
  73         self.assertStatement(stmt, [C(2,  4), C(1,  4)], C(2,   8))
  74         self.assertStatement(stmt, [C(2,  4), C(2,  4)], C(4,   8))
  75         self.assertStatement(stmt, [C(7,  4), C(7,  4)], C(49,  8))
  76
  77     def test_and(self):
  78         stmt = lambda y, a, b: y.eq(a & b)
  79         self.assertStatement(stmt, [C(0b1100, 4), C(0b1010, 4)], C(0b1000, 4))
  80
  81     def test_or(self):
  82         stmt = lambda y, a, b: y.eq(a | b)
  83         self.assertStatement(stmt, [C(0b1100, 4), C(0b1010, 4)], C(0b1110, 4))
  84
  85     def test_xor(self):
  86         stmt = lambda y, a, b: y.eq(a ^ b)
  87         self.assertStatement(stmt, [C(0b1100, 4), C(0b1010, 4)], C(0b0110, 4))
  88
  89     def test_shl(self):
  90         stmt = lambda y, a, b: y.eq(a << b)
  91         self.assertStatement(stmt, [C(0b1001, 4), C(0)],  C(0b1001,    5))
  92         self.assertStatement(stmt, [C(0b1001, 4), C(3)],  C(0b1001000, 7))
  93         self.assertStatement(stmt, [C(0b1001, 4), C(-2)], C(0b10,      7))
  94
  95     def test_shr(self):
  96         stmt = lambda y, a, b: y.eq(a >> b)
  97         self.assertStatement(stmt, [C(0b1001, 4), C(0)],  C(0b1001,    4))
  98         self.assertStatement(stmt, [C(0b1001, 4), C(2)],  C(0b10,      4))
  99         self.assertStatement(stmt, [C(0b1001, 4), C(-2)], C(0b100100,  5))
 100
 101     def test_eq(self):
 102         stmt = lambda y, a, b: y.eq(a == b)
 103         self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(1))
 104         self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(0))
 105         self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(0))
 106
 107     def test_ne(self):
 108         stmt = lambda y, a, b: y.eq(a != b)
 109         self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(0))
 110         self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(1))
 111         self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(1))
 112
 113     def test_lt(self):
 114         stmt = lambda y, a, b: y.eq(a < b)
 115         self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(0))
 116         self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(1))
 117         self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(0))
 118
 119     def test_ge(self):
 120         stmt = lambda y, a, b: y.eq(a >= b)
 121         self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(1))
 122         self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(0))
 123         self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(1))
 124
 125     def test_gt(self):
 126         stmt = lambda y, a, b: y.eq(a > b)
 127         self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(0))
 128         self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(0))
 129         self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(1))
 130
 131     def test_le(self):
 132         stmt = lambda y, a, b: y.eq(a <= b)
 133         self.assertStatement(stmt, [C(0, 4), C(0, 4)], C(1))
 134         self.assertStatement(stmt, [C(0, 4), C(1, 4)], C(1))
 135         self.assertStatement(stmt, [C(1, 4), C(0, 4)], C(0))
 136
 137     def test_mux(self):
 138         stmt = lambda y, a, b, c: y.eq(Mux(c, a, b))
 139         self.assertStatement(stmt, [C(2, 4), C(3, 4), C(0)], C(3, 4))
 140         self.assertStatement(stmt, [C(2, 4), C(3, 4), C(1)], C(2, 4))
 141
 142     def test_slice(self):
 143         stmt1 = lambda y, a: y.eq(a[2])
 144         self.assertStatement(stmt1, [C(0b10110100, 8)], C(0b1,  1))
 145         stmt2 = lambda y, a: y.eq(a[2:4])
 146         self.assertStatement(stmt2, [C(0b10110100, 8)], C(0b01, 2))
 147
 148     def test_slice_lhs(self):
 149         stmt1 = lambda y, a: y[2].eq(a)
 150         self.assertStatement(stmt1, [C(0b0,  1)], C(0b11111011, 8), reset=0b11111111)
 151         stmt2 = lambda y, a: y[2:4].eq(a)
 152         self.assertStatement(stmt2, [C(0b01, 2)], C(0b11110111, 8), reset=0b11111011)
 153
 154     def test_part(self):
 155         stmt = lambda y, a, b: y.eq(a.part(b, 3))
 156         self.assertStatement(stmt, [C(0b10110100, 8), C(0)], C(0b100, 3))
 157         self.assertStatement(stmt, [C(0b10110100, 8), C(2)], C(0b101, 3))
 158         self.assertStatement(stmt, [C(0b10110100, 8), C(3)], C(0b110, 3))
 159
 160     def test_part_lhs(self):
 161         stmt = lambda y, a, b: y.part(a, 3).eq(b)
 162         self.assertStatement(stmt, [C(0), C(0b100, 3)], C(0b11111100, 8), reset=0b11111111)
 163         self.assertStatement(stmt, [C(2), C(0b101, 3)], C(0b11110111, 8), reset=0b11111111)
 164         self.assertStatement(stmt, [C(3), C(0b110, 3)], C(0b11110111, 8), reset=0b11111111)
 165
 166     def test_cat(self):
 167         stmt = lambda y, *xs: y.eq(Cat(*xs))
 168         self.assertStatement(stmt, [C(0b10, 2), C(0b01, 2)], C(0b0110, 4))
 169
 170     def test_cat_lhs(self):
 171         l = Signal(3)
 172         m = Signal(3)
 173         n = Signal(3)
 174         stmt = lambda y, a: [Cat(l, m, n).eq(a), y.eq(Cat(n, m, l))]
 175         self.assertStatement(stmt, [C(0b100101110, 9)], C(0b110101100, 9))
 176
 177     def test_record(self):
 178         rec = Record([
 179             ("l", 1),
 180             ("m", 2),
 181         ])
 182         stmt = lambda y, a: [rec.eq(a), y.eq(rec)]
 183         self.assertStatement(stmt, [C(0b101, 3)], C(0b101, 3))
 184
 185     def test_repl(self):
 186         stmt = lambda y, a: y.eq(Repl(a, 3))
 187         self.assertStatement(stmt, [C(0b10, 2)], C(0b101010, 6))
 188
 189     def test_array(self):
 190         array = Array([1, 4, 10])
 191         stmt = lambda y, a: y.eq(array[a])
 192         self.assertStatement(stmt, [C(0)], C(1))
 193         self.assertStatement(stmt, [C(1)], C(4))
 194         self.assertStatement(stmt, [C(2)], C(10))
 195
 196     def test_array_oob(self):
 197         array = Array([1, 4, 10])
 198         stmt = lambda y, a: y.eq(array[a])
 199         self.assertStatement(stmt, [C(3)], C(10))
 200         self.assertStatement(stmt, [C(4)], C(10))
 201
 202     def test_array_lhs(self):
 203         l = Signal(3, reset=1)
 204         m = Signal(3, reset=4)
 205         n = Signal(3, reset=7)
 206         array = Array([l, m, n])
 207         stmt = lambda y, a, b: [array[a].eq(b), y.eq(Cat(*array))]
 208         self.assertStatement(stmt, [C(0), C(0b000)], C(0b111100000))
 209         self.assertStatement(stmt, [C(1), C(0b010)], C(0b111010001))
 210         self.assertStatement(stmt, [C(2), C(0b100)], C(0b100100001))
 211
 212     def test_array_lhs_oob(self):
 213         l = Signal(3)
 214         m = Signal(3)
 215         n = Signal(3)
 216         array = Array([l, m, n])
 217         stmt = lambda y, a, b: [array[a].eq(b), y.eq(Cat(*array))]
 218         self.assertStatement(stmt, [C(3), C(0b001)], C(0b001000000))
 219         self.assertStatement(stmt, [C(4), C(0b010)], C(0b010000000))
 220
 221     def test_array_index(self):
 222         array = Array(Array(x * y for y in range(10)) for x in range(10))
 223         stmt = lambda y, a, b: y.eq(array[a][b])
 224         for x in range(10):
 225             for y in range(10):
 226                 self.assertStatement(stmt, [C(x), C(y)], C(x * y))
 227
 228     def test_array_attr(self):
 229         from collections import namedtuple
 230         pair = namedtuple("pair", ("p", "n"))
 231
 232         array = Array(pair(x, -x) for x in range(10))
 233         stmt = lambda y, a: y.eq(array[a].p + array[a].n)
 234         for i in range(10):
 235             self.assertStatement(stmt, [C(i)], C(0))
 236
 237
 238 class SimulatorIntegrationTestCase(FHDLTestCase):
 239     @contextmanager
 240     def assertSimulation(self, module, deadline=None):
 241         with Simulator(module.elaborate(platform=None)) as sim:
 242             yield sim
 243             if deadline is None:
 244                 sim.run()
 245             else:
 246                 sim.run_until(deadline)
 247
 248     def setUp_counter(self):
 249         self.count = Signal(3, reset=4)
 250         self.sync  = ClockDomain()
 251
 252         self.m = Module()
 253         self.m.d.sync  += self.count.eq(self.count + 1)
 254         self.m.domains += self.sync
 255
 256     def test_counter_process(self):
 257         self.setUp_counter()
 258         with self.assertSimulation(self.m) as sim:
 259             def process():
 260                 self.assertEqual((yield self.count), 4)
 261                 yield Delay(1e-6)
 262                 self.assertEqual((yield self.count), 4)
 263                 yield self.sync.clk.eq(1)
 264                 self.assertEqual((yield self.count), 5)
 265                 yield Delay(1e-6)
 266                 self.assertEqual((yield self.count), 5)
 267                 yield self.sync.clk.eq(0)
 268                 self.assertEqual((yield self.count), 5)
 269                 for _ in range(3):
 270                     yield Delay(1e-6)
 271                     yield self.sync.clk.eq(1)
 272                     yield Delay(1e-6)
 273                     yield self.sync.clk.eq(0)
 274                 self.assertEqual((yield self.count), 0)
 275             sim.add_process(process)
 276
 277     def test_counter_clock_and_sync_process(self):
 278         self.setUp_counter()
 279         with self.assertSimulation(self.m) as sim:
 280             sim.add_clock(1e-6, domain="sync")
 281             def process():
 282                 self.assertEqual((yield self.count), 4)
 283                 self.assertEqual((yield self.sync.clk), 1)
 284                 yield
 285                 self.assertEqual((yield self.count), 5)
 286                 self.assertEqual((yield self.sync.clk), 1)
 287                 for _ in range(3):
 288                     yield
 289                 self.assertEqual((yield self.count), 0)
 290             sim.add_sync_process(process)
 291
 292     def setUp_alu(self):
 293         self.a = Signal(8)
 294         self.b = Signal(8)
 295         self.o = Signal(8)
 296         self.x = Signal(8)
 297         self.s = Signal(2)
 298         self.sync = ClockDomain(reset_less=True)
 299
 300         self.m = Module()
 301         self.m.d.comb += self.x.eq(self.a ^ self.b)
 302         with self.m.Switch(self.s):
 303             with self.m.Case(0):
 304                 self.m.d.sync += self.o.eq(self.a + self.b)
 305             with self.m.Case(1):
 306                 self.m.d.sync += self.o.eq(self.a - self.b)
 307             with self.m.Case():
 308                 self.m.d.sync += self.o.eq(0)
 309         self.m.domains += self.sync
 310
 311     def test_alu(self):
 312         self.setUp_alu()
 313         with self.assertSimulation(self.m) as sim:
 314             sim.add_clock(1e-6)
 315             def process():
 316                 yield self.a.eq(5)
 317                 yield self.b.eq(1)
 318                 yield
 319                 self.assertEqual((yield self.x), 4)
 320                 yield
 321                 self.assertEqual((yield self.o), 6)
 322                 yield self.s.eq(1)
 323                 yield
 324                 yield
 325                 self.assertEqual((yield self.o), 4)
 326                 yield self.s.eq(2)
 327                 yield
 328                 yield
 329                 self.assertEqual((yield self.o), 0)
 330             sim.add_sync_process(process)
 331
 332     def setUp_multiclock(self):
 333         self.sys = ClockDomain()
 334         self.pix = ClockDomain()
 335
 336         self.m = Module()
 337         self.m.domains += self.sys, self.pix
 338
 339     def test_multiclock(self):
 340         self.setUp_multiclock()
 341         with self.assertSimulation(self.m) as sim:
 342             sim.add_clock(1e-6, domain="sys")
 343             sim.add_clock(0.3e-6, domain="pix")
 344
 345             def sys_process():
 346                 yield Passive()
 347                 yield
 348                 yield
 349                 self.fail()
 350             def pix_process():
 351                 yield
 352                 yield
 353                 yield
 354             sim.add_sync_process(sys_process, domain="sys")
 355             sim.add_sync_process(pix_process, domain="pix")
 356
 357     def setUp_lhs_rhs(self):
 358         self.i = Signal(8)
 359         self.o = Signal(8)
 360
 361         self.m = Module()
 362         self.m.d.comb += self.o.eq(self.i)
 363
 364     def test_complex_lhs_rhs(self):
 365         self.setUp_lhs_rhs()
 366         with self.assertSimulation(self.m) as sim:
 367             def process():
 368                 yield self.i.eq(0b10101010)
 369                 yield self.i[:4].eq(-1)
 370                 yield Delay()
 371                 self.assertEqual((yield self.i[:4]), 0b1111)
 372                 self.assertEqual((yield self.i), 0b10101111)
 373             sim.add_process(process)
 374
 375     def test_run_until(self):
 376         with self.assertSimulation(Module(), deadline=100e-6) as sim:
 377             sim.add_clock(1e-6)
 378             def process():
 379                 for _ in range(100):
 380                     yield
 381                 self.fail()
 382
 383     def test_add_process_wrong(self):
 384         with self.assertSimulation(Module()) as sim:
 385             with self.assertRaises(TypeError,
 386                     msg="Cannot add a process '1' because it is not a generator or "
 387                         "a generator function"):
 388                 sim.add_process(1)
 389
 390     def test_eq_signal_unused_wrong(self):
 391         self.setUp_lhs_rhs()
 392         self.s = Signal()
 393         with self.assertSimulation(self.m) as sim:
 394             def process():
 395                 with self.assertRaisesRegex(ValueError,
 396                         regex=r"Process '.+?' sent a request to set signal '\(sig s\)', "
 397                               r"which is not a part of simulation"):
 398                     yield self.s.eq(0)
 399                 yield Delay()
 400             sim.add_process(process)
 401
 402     def test_eq_signal_comb_wrong(self):
 403         self.setUp_lhs_rhs()
 404         with self.assertSimulation(self.m) as sim:
 405             def process():
 406                 with self.assertRaisesRegex(ValueError,
 407                         regex=r"Process '.+?' sent a request to set signal '\(sig o\)', "
 408                               r"which is a part of combinatorial assignment in simulation"):
 409                     yield self.o.eq(0)
 410                 yield Delay()
 411             sim.add_process(process)
 412
 413     def test_command_wrong(self):
 414         with self.assertSimulation(Module()) as sim:
 415             def process():
 416                 with self.assertRaisesRegex(TypeError,
 417                         regex=r"Received unsupported command '1' from process '.+?'"):
 418                     yield 1
 419                 yield Delay()
 420             sim.add_process(process)
 421
 422     def setUp_memory(self, rd_synchronous=True, rd_transparent=True, wr_granularity=None):
 423         self.m = Module()
 424         self.memory = Memory(width=8, depth=4, init=[0xaa, 0x55])
 425         self.m.submodules.rdport = self.rdport = \
 426             self.memory.read_port(synchronous=rd_synchronous, transparent=rd_transparent)
 427         self.m.submodules.wrport = self.wrport = \
 428             self.memory.write_port(granularity=wr_granularity)
 429
 430     def test_memory_init(self):
 431         self.setUp_memory()
 432         with self.assertSimulation(self.m) as sim:
 433             def process():
 434                 self.assertEqual((yield self.rdport.data), 0xaa)
 435                 yield self.rdport.addr.eq(1)
 436                 yield
 437                 yield
 438                 self.assertEqual((yield self.rdport.data), 0x55)
 439                 yield self.rdport.addr.eq(2)
 440                 yield
 441                 yield
 442                 self.assertEqual((yield self.rdport.data), 0x00)
 443             sim.add_clock(1e-6)
 444             sim.add_sync_process(process)
 445
 446     def test_memory_write(self):
 447         self.setUp_memory()
 448         with self.assertSimulation(self.m) as sim:
 449             def process():
 450                 yield self.wrport.addr.eq(4)
 451                 yield self.wrport.data.eq(0x33)
 452                 yield self.wrport.en.eq(1)
 453                 yield
 454                 yield self.wrport.en.eq(0)
 455                 yield self.rdport.addr.eq(4)
 456                 yield
 457                 self.assertEqual((yield self.rdport.data), 0x33)
 458             sim.add_clock(1e-6)
 459             sim.add_sync_process(process)
 460
 461     def test_memory_write_granularity(self):
 462         self.setUp_memory(wr_granularity=4)
 463         with self.assertSimulation(self.m) as sim:
 464             def process():
 465                 yield self.wrport.data.eq(0x50)
 466                 yield self.wrport.en.eq(0b00)
 467                 yield
 468                 yield self.wrport.en.eq(0)
 469                 yield
 470                 self.assertEqual((yield self.rdport.data), 0xaa)
 471                 yield self.wrport.en.eq(0b10)
 472                 yield
 473                 yield self.wrport.en.eq(0)
 474                 yield
 475                 self.assertEqual((yield self.rdport.data), 0x5a)
 476                 yield self.wrport.data.eq(0x33)
 477                 yield self.wrport.en.eq(0b01)
 478                 yield
 479                 yield self.wrport.en.eq(0)
 480                 yield
 481                 self.assertEqual((yield self.rdport.data), 0x53)
 482             sim.add_clock(1e-6)
 483             sim.add_sync_process(process)
 484
 485     def test_memory_read_before_write(self):
 486         self.setUp_memory(rd_transparent=False)
 487         with self.assertSimulation(self.m) as sim:
 488             def process():
 489                 yield self.wrport.data.eq(0x33)
 490                 yield self.wrport.en.eq(1)
 491                 yield self.rdport.en.eq(1)
 492                 yield
 493                 self.assertEqual((yield self.rdport.data), 0x00)
 494                 yield
 495                 self.assertEqual((yield self.rdport.data), 0xaa)
 496                 yield Delay(1e-6) # let comb propagate
 497                 self.assertEqual((yield self.rdport.data), 0x33)
 498             sim.add_clock(1e-6)
 499             sim.add_sync_process(process)
 500
 501     def test_memory_write_through(self):
 502         self.setUp_memory(rd_transparent=True)
 503         with self.assertSimulation(self.m) as sim:
 504             def process():
 505                 yield self.wrport.data.eq(0x33)
 506                 yield self.wrport.en.eq(1)
 507                 yield
 508                 self.assertEqual((yield self.rdport.data), 0xaa)
 509                 yield Delay(1e-6) # let comb propagate
 510                 self.assertEqual((yield self.rdport.data), 0x33)
 511                 yield
 512                 yield self.rdport.addr.eq(1)
 513                 yield Delay(1e-6) # let comb propagate
 514                 self.assertEqual((yield self.rdport.data), 0x33)
 515             sim.add_clock(1e-6)
 516             sim.add_sync_process(process)
 517
 518     def test_memory_async_read_write(self):
 519         self.setUp_memory(rd_synchronous=False)
 520         with self.assertSimulation(self.m) as sim:
 521             def process():
 522                 yield self.rdport.addr.eq(0)
 523                 yield Delay()
 524                 self.assertEqual((yield self.rdport.data), 0xaa)
 525                 yield self.rdport.addr.eq(1)
 526                 yield Delay()
 527                 self.assertEqual((yield self.rdport.data), 0x55)
 528                 yield self.rdport.addr.eq(0)
 529                 yield self.wrport.addr.eq(0)
 530                 yield self.wrport.data.eq(0x33)
 531                 yield self.wrport.en.eq(1)
 532                 yield Tick("sync")
 533                 self.assertEqual((yield self.rdport.data), 0xaa)
 534                 yield Delay(1e-6) # let comb propagate
 535                 self.assertEqual((yield self.rdport.data), 0x33)
 536             sim.add_clock(1e-6)
 537             sim.add_process(process)
 538
 539     def test_memory_read_only(self):
 540         self.m = Module()
 541         self.memory = Memory(width=8, depth=4, init=[0xaa, 0x55])
 542         self.m.submodules.rdport = self.rdport = self.memory.read_port()
 543         with self.assertSimulation(self.m) as sim:
 544             def process():
 545                 self.assertEqual((yield self.rdport.data), 0xaa)
 546                 yield self.rdport.addr.eq(1)
 547                 yield
 548                 yield
 549                 self.assertEqual((yield self.rdport.data), 0x55)
 550             sim.add_clock(1e-6)
 551             sim.add_sync_process(process)
 552
 553     def test_sample_helpers(self):
 554         m = Module()
 555         s = Signal(2)
 556         def mk(x):
 557             y = Signal.like(x)
 558             m.d.comb += y.eq(x)
 559             return y
 560         p0, r0, f0, s0 = mk(Past(s, 0)), mk(Rose(s)),    mk(Fell(s)),    mk(Stable(s))
 561         p1, r1, f1, s1 = mk(Past(s)),    mk(Rose(s, 1)), mk(Fell(s, 1)), mk(Stable(s, 1))
 562         p2, r2, f2, s2 = mk(Past(s, 2)), mk(Rose(s, 2)), mk(Fell(s, 2)), mk(Stable(s, 2))
 563         p3, r3, f3, s3 = mk(Past(s, 3)), mk(Rose(s, 3)), mk(Fell(s, 3)), mk(Stable(s, 3))
 564         with self.assertSimulation(m) as sim:
 565             def process_gen():
 566                 yield s.eq(0b10)
 567                 yield
 568                 yield
 569                 yield s.eq(0b01)
 570                 yield
 571             def process_check():
 572                 yield
 573                 yield
 574                 yield
 575
 576                 self.assertEqual((yield p0), 0b01)
 577                 self.assertEqual((yield p1), 0b10)
 578                 self.assertEqual((yield p2), 0b10)
 579                 self.assertEqual((yield p3), 0b00)
 580
 581                 self.assertEqual((yield s0), 0b0)
 582                 self.assertEqual((yield s1), 0b1)
 583                 self.assertEqual((yield s2), 0b0)
 584                 self.assertEqual((yield s3), 0b1)
 585
 586                 self.assertEqual((yield r0), 0b01)
 587                 self.assertEqual((yield r1), 0b00)
 588                 self.assertEqual((yield r2), 0b10)
 589                 self.assertEqual((yield r3), 0b00)
 590
 591                 self.assertEqual((yield f0), 0b10)
 592                 self.assertEqual((yield f1), 0b00)
 593                 self.assertEqual((yield f2), 0b00)
 594                 self.assertEqual((yield f3), 0b00)
 595             sim.add_clock(1e-6)
 596             sim.add_sync_process(process_gen)
 597             sim.add_sync_process(process_check)
 598
 599     def test_wrong_not_run(self):
 600         with self.assertWarns(UserWarning,
 601                 msg="Simulation created, but not run"):
 602             with Simulator(Fragment()) as sim:
 603                 pass