vendor.xilinx_{7series,ultrascale}: don't use `write_verilog -decimal`.
[nmigen.git] / nmigen / utils.py
1 __all__ = ["log2_int", "bits_for"]
2
3
4 def log2_int(n, need_pow2=True):
5 if n == 0:
6 return 0
7 r = (n - 1).bit_length()
8 if need_pow2 and (1 << r) != n:
9 raise ValueError("{} is not a power of 2".format(n))
10 return r
11
12
13 def bits_for(n, require_sign_bit=False):
14 if n > 0:
15 r = log2_int(n + 1, False)
16 else:
17 require_sign_bit = True
18 r = log2_int(-n, False)
19 if require_sign_bit:
20 r += 1
21 return r