1 from abc
import abstractproperty
7 __all__
= ["LatticeECP5Platform"]
10 class LatticeECP5Platform(TemplatedPlatform
):
20 The environment is populated by running the script specified in the environment variable
21 ``NMIGEN_ENV_Trellis``, if present.
24 * ``verbose``: enables logging of informational messages to standard error.
25 * ``read_verilog_opts``: adds options for ``read_verilog`` Yosys command.
26 * ``synth_opts``: adds options for ``synth_ecp5`` Yosys command.
27 * ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
28 * ``script_after_synth``: inserts commands after ``synth_ecp5`` in Yosys script.
29 * ``yosys_opts``: adds extra options for ``yosys``.
30 * ``nextpnr_opts``: adds extra options for ``nextpnr-ecp5``.
31 * ``ecppack_opts``: adds extra options for ``ecppack``.
32 * ``add_preferences``: inserts commands at the end of the LPF file.
35 * ``{{name}}.rpt``: Yosys log.
36 * ``{{name}}.json``: synthesized RTL.
37 * ``{{name}}.tim``: nextpnr log.
38 * ``{{name}}.config``: ASCII bitstream.
39 * ``{{name}}.bit``: binary bitstream.
40 * ``{{name}}.svf``: JTAG programming vector.
49 The environment is populated by running the script specified in the environment variable
50 ``NMIGEN_ENV_Diamond``, if present. On Linux, diamond_env as provided by Diamond
51 itself is a good candidate. On Windows, the following script (named ``diamond_env.bat``,
52 for instance) is known to work::
55 set PATH=C:\\lscc\\diamond\\%DIAMOND_VERSION%\\bin\\nt64;%PATH%
58 * ``script_project``: inserts commands before ``prj_project save`` in Tcl script.
59 * ``script_after_export``: inserts commands after ``prj_run Export`` in Tcl script.
60 * ``add_preferences``: inserts commands at the end of the LPF file.
61 * ``add_constraints``: inserts commands at the end of the XDC file.
64 * ``{{name}}_impl/{{name}}_impl.htm``: consolidated log.
65 * ``{{name}}.bit``: binary bitstream.
66 * ``{{name}}.svf``: JTAG programming vector.
69 toolchain
= None # selected when creating platform
71 device
= abstractproperty()
72 package
= abstractproperty()
73 speed
= abstractproperty()
74 grade
= "C" # [C]ommercial, [I]ndustrial
78 _nextpnr_device_options
= {
83 "LFE5UM-25F": "--um-25k",
84 "LFE5UM-45F": "--um-45k",
85 "LFE5UM-85F": "--um-85k",
86 "LFE5UM5G-25F": "--um5g-25k",
87 "LFE5UM5G-45F": "--um5g-45k",
88 "LFE5UM5G-85F": "--um5g-85k",
90 _nextpnr_package_options
= {
98 _trellis_required_tools
= [
103 _trellis_file_templates
= {
104 **TemplatedPlatform
.build_script_templates
,
109 "{{name}}.debug.v": r
"""
110 /* {{autogenerated}} */
111 {{emit_debug_verilog()}}
115 {% for file in platform.iter_files(".v") -%}
116 read_verilog {{get_override("read_verilog_opts")|options}} {{file}}
118 {% for file in platform.iter_files(".sv") -%}
119 read_verilog -sv {{get_override("read_verilog_opts")|options}} {{file}}
121 {% for file in platform.iter_files(".il") -%}
124 read_ilang {{name}}.il
125 delete w:$verilog_initial_trigger
126 {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
127 synth_ecp5 {{get_override("synth_opts")|options}} -top {{name}}
128 {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
129 write_json {{name}}.json
135 {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
136 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
138 IOBUF PORT "{{port_name}}"
139 {%- for key, value in attrs.items() %} {{key}}={{value}}{% endfor %};
142 {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
143 {% if port_signal is not none -%}
144 FREQUENCY PORT "{{port_signal.name}}" {{frequency}} HZ;
146 FREQUENCY NET "{{net_signal|hierarchy(".")}}" {{frequency}} HZ;
149 {{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
152 _trellis_command_templates
= [
154 {{invoke_tool("yosys")}}
156 {{get_override("yosys_opts")|options}}
161 {{invoke_tool("nextpnr-ecp5")}}
163 {{get_override("nextpnr_opts")|options}}
165 {{platform._nextpnr_device_options[platform.device]}}
166 --package {{platform._nextpnr_package_options[platform.package]|upper}}
167 --speed {{platform.speed}}
170 --textcfg {{name}}.config
173 {{invoke_tool("ecppack")}}
174 {{verbose("--verbose")}}
175 {{get_override("ecppack_opts")|options}}
176 --input {{name}}.config
184 _diamond_required_tools
= [
188 _diamond_file_templates
= {
189 **TemplatedPlatform
.build_script_templates
,
190 "build_{{name}}.sh": r
"""
192 set -e{{verbose("x")}}
193 if [ -z "$BASH" ] ; then exec /bin/bash "$0" "$@"; fi
194 if [ -n "${{platform._toolchain_env_var}}" ]; then
195 bindir=$(dirname "${{platform._toolchain_env_var}}")
196 . "${{platform._toolchain_env_var}}"
198 {{emit_commands("sh")}}
201 /* {{autogenerated}} */
204 "{{name}}.debug.v": r
"""
205 /* {{autogenerated}} */
206 {{emit_debug_verilog()}}
209 prj_project new -name {{name}} -impl impl -impl_dir {{name}}_impl \
210 -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \
213 {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%}
214 prj_src add {{file|tcl_escape}}
216 prj_src add {{name}}.v
217 prj_impl option top {{name}}
218 prj_src add {{name}}.sdc
219 {{get_override("script_project")|default("# (script_project placeholder)")}}
221 prj_run Synthesis -impl impl -forceAll
222 prj_run Translate -impl impl -forceAll
223 prj_run Map -impl impl -forceAll
224 prj_run PAR -impl impl -forceAll
225 prj_run Export -impl impl -forceAll -task Bitgen
226 {{get_override("script_after_export")|default("# (script_after_export placeholder)")}}
232 {% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
233 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
234 IOBUF PORT "{{port_name}}"
235 {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
237 {{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
240 {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
241 {% if port_signal is not none -%}
242 create_clock -name {{port_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_escape}}]
244 create_clock -name {{net_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_escape}}]
247 {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
250 _diamond_command_templates
= [
251 # These don't have any usable command-line option overrides.
253 {{invoke_tool("pnmainc")}}
257 {{invoke_tool("ddtcmd")}}
259 -if {{name}}_impl/{{name}}_impl.bit -of {{name}}.bit
262 {{invoke_tool("ddtcmd")}}
263 -oft -svfsingle -revd -op "Fast Program"
264 -if {{name}}_impl/{{name}}_impl.bit -of {{name}}.svf
270 def __init__(self
, *, toolchain
="Trellis"):
273 assert toolchain
in ("Trellis", "Diamond")
274 self
.toolchain
= toolchain
277 def required_tools(self
):
278 if self
.toolchain
== "Trellis":
279 return self
._trellis
_required
_tools
280 if self
.toolchain
== "Diamond":
281 return self
._diamond
_required
_tools
285 def file_templates(self
):
286 if self
.toolchain
== "Trellis":
287 return self
._trellis
_file
_templates
288 if self
.toolchain
== "Diamond":
289 return self
._diamond
_file
_templates
293 def command_templates(self
):
294 if self
.toolchain
== "Trellis":
295 return self
._trellis
_command
_templates
296 if self
.toolchain
== "Diamond":
297 return self
._diamond
_command
_templates
301 def default_clk_constraint(self
):
302 if self
.default_clk
== "OSCG":
303 return Clock(310e6
/ self
.oscg_div
)
304 return super().default_clk_constraint
306 def create_missing_domain(self
, name
):
307 # Lattice ECP5 devices have two global set/reset signals: PUR, which is driven at startup
308 # by the configuration logic and unconditionally resets every storage element, and GSR,
309 # which is driven by user logic and each storage element may be configured as affected or
310 # unaffected by GSR. PUR is purely asynchronous, so even though it is a low-skew global
311 # network, its deassertion may violate a setup/hold constraint with relation to a user
312 # clock. To avoid this, a GSR/SGSR instance should be driven synchronized to user clock.
313 if name
== "sync" and self
.default_clk
is not None:
315 if self
.default_clk
== "OSCG":
316 if not hasattr(self
, "oscg_div"):
317 raise ValueError("OSCG divider (oscg_div) must be an integer between 2 "
319 if not isinstance(self
.oscg_div
, int) or self
.oscg_div
< 2 or self
.oscg_div
> 128:
320 raise ValueError("OSCG divider (oscg_div) must be an integer between 2 "
322 .format(self
.oscg_div
))
324 m
.submodules
+= Instance("OSCG", p_DIV
=self
.oscg_div
, o_OSC
=clk_i
)
326 clk_i
= self
.request(self
.default_clk
).i
327 if self
.default_rst
is not None:
328 rst_i
= self
.request(self
.default_rst
).i
334 # There is no end-of-startup signal on ECP5, but PUR is released after IOB enable, so
335 # a simple reset synchronizer (with PUR as the asynchronous reset) does the job.
337 Instance("FD1S3AX", p_GSR
="DISABLED", i_CK
=clk_i
, i_D
=~rst_i
, o_Q
=gsr0
),
338 Instance("FD1S3AX", p_GSR
="DISABLED", i_CK
=clk_i
, i_D
=gsr0
, o_Q
=gsr1
),
339 # Although we already synchronize the reset input to user clock, SGSR has dedicated
340 # clock routing to the center of the FPGA; use that just in case it turns out to be
341 # more reliable. (None of this is documented.)
342 Instance("SGSR", i_CLK
=clk_i
, i_GSR
=gsr1
),
344 # GSR implicitly connects to every appropriate storage element. As such, the sync
345 # domain is reset-less; domains driven by other clocks would need to have dedicated
346 # reset circuitry or otherwise meet setup/hold constraints on their own.
347 m
.domains
+= ClockDomain("sync", reset_less
=True)
348 m
.d
.comb
+= ClockSignal("sync").eq(clk_i
)
351 _single_ended_io_types
= [
352 "HSUL12", "LVCMOS12", "LVCMOS15", "LVCMOS18", "LVCMOS25", "LVCMOS33", "LVTTL33",
353 "SSTL135_I", "SSTL135_II", "SSTL15_I", "SSTL15_II", "SSTL18_I", "SSTL18_II",
355 _differential_io_types
= [
356 "BLVDS25", "BLVDS25E", "HSUL12D", "LVCMOS18D", "LVCMOS25D", "LVCMOS33D",
357 "LVDS", "LVDS25E", "LVPECL33", "LVPECL33E", "LVTTL33D", "MLVDS", "MLVDS25E",
358 "SLVS", "SSTL135D_I", "SSTL135D_II", "SSTL15D_I", "SSTL15D_II", "SSTL18D_I",
359 "SSTL18D_II", "SUBLVDS",
362 def should_skip_port_component(self
, port
, attrs
, component
):
363 # On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at
364 # the PIOA or PIOC location, which is always the non-inverting pin.
365 if attrs
.get("IO_TYPE", "LVCMOS25") in self
._differential
_io
_types
and component
== "n":
369 def _get_xdr_buffer(self
, m
, pin
, *, i_invert
=False, o_invert
=False):
370 def get_ireg(clk
, d
, q
):
371 for bit
in range(len(q
)):
372 m
.submodules
+= Instance("IFS1P3DX",
380 def get_oreg(clk
, d
, q
):
381 for bit
in range(len(q
)):
382 m
.submodules
+= Instance("OFS1P3DX",
390 def get_iddr(sclk
, d
, q0
, q1
):
391 for bit
in range(len(d
)):
392 m
.submodules
+= Instance("IDDRX1F",
396 o_Q0
=q0
[bit
], o_Q1
=q1
[bit
]
399 def get_iddrx2(sclk
, eclk
, d
, q0
, q1
, q2
, q3
):
400 for bit
in range(len(d
)):
401 m
.submodules
+= Instance("IDDRX2F",
406 o_Q0
=q0
[bit
], o_Q1
=q1
[bit
], o_Q2
=q2
[bit
], o_Q3
=q3
[bit
]
409 def get_iddr71b(sclk
, eclk
, d
, q0
, q1
, q2
, q3
, q4
, q5
, q6
):
410 for bit
in range(len(d
)):
411 m
.submodules
+= Instance("IDDR71B",
416 o_Q0
=q0
[bit
], o_Q1
=q1
[bit
], o_Q2
=q2
[bit
], o_Q3
=q3
[bit
],
417 o_Q4
=q4
[bit
], o_Q5
=q5
[bit
], o_Q6
=q6
[bit
],
420 def get_oddr(sclk
, d0
, d1
, q
):
421 for bit
in range(len(q
)):
422 m
.submodules
+= Instance("ODDRX1F",
425 i_D0
=d0
[bit
], i_D1
=d1
[bit
],
429 def get_oddrx2(sclk
, eclk
, d0
, d1
, d2
, d3
, q
):
430 for bit
in range(len(q
)):
431 m
.submodules
+= Instance("ODDRX2F",
435 i_D0
=d0
[bit
], i_D1
=d1
[bit
], i_D2
=d2
[bit
], i_D3
=d3
[bit
],
439 def get_oddr71b(sclk
, eclk
, d0
, d1
, d2
, d3
, d4
, d5
, d6
, q
):
440 for bit
in range(len(q
)):
441 m
.submodules
+= Instance("ODDR71B",
445 i_D0
=d0
[bit
], i_D1
=d1
[bit
], i_D2
=d2
[bit
], i_D3
=d3
[bit
],
446 i_D4
=d4
[bit
], i_D5
=d5
[bit
], i_D6
=d6
[bit
],
450 def get_ineg(z
, invert
):
452 a
= Signal
.like(z
, name_suffix
="_n")
458 def get_oneg(a
, invert
):
460 z
= Signal
.like(a
, name_suffix
="_n")
468 pin_i
= get_ineg(pin
.i
, i_invert
)
470 pin_i0
= get_ineg(pin
.i0
, i_invert
)
471 pin_i1
= get_ineg(pin
.i1
, i_invert
)
473 pin_i0
= get_ineg(pin
.i0
, i_invert
)
474 pin_i1
= get_ineg(pin
.i1
, i_invert
)
475 pin_i2
= get_ineg(pin
.i2
, i_invert
)
476 pin_i3
= get_ineg(pin
.i3
, i_invert
)
478 pin_i0
= get_ineg(pin
.i0
, i_invert
)
479 pin_i1
= get_ineg(pin
.i1
, i_invert
)
480 pin_i2
= get_ineg(pin
.i2
, i_invert
)
481 pin_i3
= get_ineg(pin
.i3
, i_invert
)
482 pin_i4
= get_ineg(pin
.i4
, i_invert
)
483 pin_i5
= get_ineg(pin
.i5
, i_invert
)
484 pin_i6
= get_ineg(pin
.i6
, i_invert
)
487 pin_o
= get_oneg(pin
.o
, o_invert
)
489 pin_o0
= get_oneg(pin
.o0
, o_invert
)
490 pin_o1
= get_oneg(pin
.o1
, o_invert
)
492 pin_o0
= get_oneg(pin
.o0
, o_invert
)
493 pin_o1
= get_oneg(pin
.o1
, o_invert
)
494 pin_o2
= get_oneg(pin
.o2
, o_invert
)
495 pin_o3
= get_oneg(pin
.o3
, o_invert
)
497 pin_o0
= get_oneg(pin
.o0
, o_invert
)
498 pin_o1
= get_oneg(pin
.o1
, o_invert
)
499 pin_o2
= get_oneg(pin
.o2
, o_invert
)
500 pin_o3
= get_oneg(pin
.o3
, o_invert
)
501 pin_o4
= get_oneg(pin
.o4
, o_invert
)
502 pin_o5
= get_oneg(pin
.o5
, o_invert
)
503 pin_o6
= get_oneg(pin
.o6
, o_invert
)
507 i
= Signal(pin
.width
, name
="{}_xdr_i".format(pin
.name
))
509 o
= Signal(pin
.width
, name
="{}_xdr_o".format(pin
.name
))
510 if pin
.dir in ("oe", "io"):
511 t
= Signal(1, name
="{}_xdr_t".format(pin
.name
))
518 if pin
.dir in ("oe", "io"):
522 get_ireg(pin
.i_clk
, i
, pin_i
)
524 get_oreg(pin
.o_clk
, pin_o
, o
)
525 if pin
.dir in ("oe", "io"):
526 get_oreg(pin
.o_clk
, ~pin
.oe
, t
)
529 get_iddr(pin
.i_clk
, i
, pin_i0
, pin_i1
)
531 get_oddr(pin
.o_clk
, pin_o0
, pin_o1
, o
)
532 if pin
.dir in ("oe", "io"):
533 # It looks like Diamond will not pack an OREG as a tristate register in a DDR PIO.
534 # It is not clear what is the recommended set of primitives for this task.
535 # Similarly, nextpnr will not pack anything as a tristate register in a DDR PIO.
536 get_oreg(pin
.o_clk
, ~pin
.oe
, t
)
539 get_iddrx2(pin
.i_clk
, pin
.i_fclk
, i
, pin_i0
, pin_i1
, pin_i2
, pin_i3
)
541 get_oddrx2(pin
.o_clk
, pin
.o_fclk
, pin_o0
, pin_o1
, pin_o2
, pin_o3
, o
)
542 if pin
.dir in ("oe", "io"):
543 get_oreg(pin
.o_clk
, ~pin
.oe
, t
)
546 get_iddr71b(pin
.i_clk
, pin
.i_fclk
, i
, pin_i0
, pin_i1
, pin_i2
, pin_i3
, pin_i4
, pin_i5
, pin_i6
)
548 get_oddr71b(pin
.o_clk
, pin
.o_fclk
, pin_o0
, pin_o1
, pin_o2
, pin_o3
, pin_o4
, pin_o5
, pin_o6
, o
)
549 if pin
.dir in ("oe", "io"):
550 get_oreg(pin
.o_clk
, ~pin
.oe
, t
)
556 def get_input(self
, pin
, port
, attrs
, invert
):
557 self
._check
_feature
("single-ended input", pin
, attrs
,
558 valid_xdrs
=(0, 1, 2, 4, 7), valid_attrs
=True)
560 i
, o
, t
= self
._get
_xdr
_buffer
(m
, pin
, i_invert
=invert
)
561 for bit
in range(pin
.width
):
562 m
.submodules
["{}_{}".format(pin
.name
, bit
)] = Instance("IB",
568 def get_output(self
, pin
, port
, attrs
, invert
):
569 self
._check
_feature
("single-ended output", pin
, attrs
,
570 valid_xdrs
=(0, 1, 2, 4, 7), valid_attrs
=True)
572 i
, o
, t
= self
._get
_xdr
_buffer
(m
, pin
, o_invert
=invert
)
573 for bit
in range(pin
.width
):
574 m
.submodules
["{}_{}".format(pin
.name
, bit
)] = Instance("OB",
580 def get_tristate(self
, pin
, port
, attrs
, invert
):
581 self
._check
_feature
("single-ended tristate", pin
, attrs
,
582 valid_xdrs
=(0, 1, 2, 4, 7), valid_attrs
=True)
584 i
, o
, t
= self
._get
_xdr
_buffer
(m
, pin
, o_invert
=invert
)
585 for bit
in range(pin
.width
):
586 m
.submodules
["{}_{}".format(pin
.name
, bit
)] = Instance("OBZ",
593 def get_input_output(self
, pin
, port
, attrs
, invert
):
594 self
._check
_feature
("single-ended input/output", pin
, attrs
,
595 valid_xdrs
=(0, 1, 2, 4, 7), valid_attrs
=True)
597 i
, o
, t
= self
._get
_xdr
_buffer
(m
, pin
, i_invert
=invert
, o_invert
=invert
)
598 for bit
in range(pin
.width
):
599 m
.submodules
["{}_{}".format(pin
.name
, bit
)] = Instance("BB",
607 def get_diff_input(self
, pin
, port
, attrs
, invert
):
608 self
._check
_feature
("differential input", pin
, attrs
,
609 valid_xdrs
=(0, 1, 2, 4, 7), valid_attrs
=True)
611 i
, o
, t
= self
._get
_xdr
_buffer
(m
, pin
, i_invert
=invert
)
612 for bit
in range(pin
.width
):
613 m
.submodules
["{}_{}".format(pin
.name
, bit
)] = Instance("IB",
619 def get_diff_output(self
, pin
, port
, attrs
, invert
):
620 self
._check
_feature
("differential output", pin
, attrs
,
621 valid_xdrs
=(0, 1, 2, 4, 7), valid_attrs
=True)
623 i
, o
, t
= self
._get
_xdr
_buffer
(m
, pin
, o_invert
=invert
)
624 for bit
in range(pin
.width
):
625 m
.submodules
["{}_{}".format(pin
.name
, bit
)] = Instance("OB",
631 def get_diff_tristate(self
, pin
, port
, attrs
, invert
):
632 self
._check
_feature
("differential tristate", pin
, attrs
,
633 valid_xdrs
=(0, 1, 2, 4, 7), valid_attrs
=True)
635 i
, o
, t
= self
._get
_xdr
_buffer
(m
, pin
, o_invert
=invert
)
636 for bit
in range(pin
.width
):
637 m
.submodules
["{}_{}".format(pin
.name
, bit
)] = Instance("OBZ",
644 def get_diff_input_output(self
, pin
, port
, attrs
, invert
):
645 self
._check
_feature
("differential input/output", pin
, attrs
,
646 valid_xdrs
=(0, 1, 2, 4, 7), valid_attrs
=True)
648 i
, o
, t
= self
._get
_xdr
_buffer
(m
, pin
, i_invert
=invert
, o_invert
=invert
)
649 for bit
in range(pin
.width
):
650 m
.submodules
["{}_{}".format(pin
.name
, bit
)] = Instance("BB",
658 # CDC primitives are not currently specialized for ECP5.
659 # While Diamond supports false path constraints; nextpnr-ecp5 does not.